STM32F103T8 STMicroelectronics, STM32F103T8 Datasheet - Page 15
Manufacturer Part Number
Mainstream Performance line, ARM Cortex-M3 MCU with 64 Kbytes Flash, 72 MHz CPU, motor control, USB and CAN
Specifications of STM32F103T8
0 to 3.6 V
timers, ADC, SPIs, I2Cs and USARTs
This hardware block provides flexible interrupt management features with minimal interrupt
External interrupt/event controller (EXTI)
The external interrupt/event controller consists of 19 edge detector lines used to generate
interrupt/event requests. Each line can be independently configured to select the trigger
event (rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 80 GPIOs can be connected
to the 16 external interrupt lines.
Clocks and startup
System clock selection is performed on startup, however the internal RC 8 MHz oscillator is
selected as default CPU clock on reset. An external 4-16 MHz clock can be selected, in
which case it is monitored for failure. If failure is detected, the system automatically switches
back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full
interrupt management of the PLL clock entry is available when necessary (for example on
failure of an indirectly used external crystal, resonator or oscillator).
Several prescalers allow the configuration of the AHB frequency, the high-speed APB
(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the AHB and
the high-speed APB domains is 72 MHz. The maximum allowed frequency of the low-speed
APB domain is 36 MHz. See
At startup, boot pins are used to select one of three boot options:
The boot loader is located in System Memory. It is used to reprogram the Flash memory by
using USART1. For further details please refer to AN2606.
Power supply schemes
For more details on how to connect power pins, refer to
Power supply supervisor
The device has an integrated power-on reset (POR)/power-down reset (PDR) circuitry. It is
always active, and ensures proper operation starting from/down to 2 V. The device remains
Boot from User Flash
Boot from System Memory
Boot from embedded SRAM
Provided externally through V
and PLL (minimum voltage to be applied to V
registers (through power switch) when V
= 2.0 to 3.6 V: external power supply for I/Os and the internal regulator.
= 1.8 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup
= 2.0 to 3.6 V: external analog power supplies for ADC, reset blocks, RCs
must be connected to V
Doc ID 13587 Rev 13
for details on the clock tree.
is not present.
is 2.4 V when the ADC is used).
Figure 13: Power supply