STM32F103ZC STMicroelectronics, STM32F103ZC Datasheet - Page 127

• Manufacturer Part Number: STM32F103ZC
• Description: Mainstream Performance line, ARM Cortex-M3 MCU with 256 Kbytes Flash, 72 MHz CPU, motor control, USB and CAN
• Manufacturer: STMicroelectronics

Specifications of STM32F103ZC

• Core: ARM 32-bit Cortex™-M3 CPU
• Conversion Range: 0 to 3.6 V
• Dma: 12-channel DMA controller
• Supported Peripherals: timers, ADCs, DAC, SDIO, I2Ss, SPIs, I2Cs and USARTs
• Systick Timer: a 24-bit downcounter

STM32F103xC, STM32F103xD, STM32F103xE
Table 75.
30-Mar-2009
Date
Document revision history
Revision
5
I/O information clarified
STM32F103xE performance line BGA100 ballout
I/O information clarified
In
– I/O level of pins PF11, PF12, PF13, PF14, PF15, G0, G1 and G15
– PB4, PB13, PB14, PB15, PB3/TRACESWO moved from Default
PG14 pin description modified in
Figure 9: Memory map on page 38
Note modified in
code with data processing running from Flash
current consumption in Sleep mode, code running from Flash or
Figure
changed).
Table 21: High-speed external user clock characteristics
Low-speed external user clock characteristics
values modified in
FSMC configuration modified for
Notes modified below
SRAM/PSRAM/NOR read waveforms
non-multiplexed SRAM/PSRAM/NOR write
t
SRAM/PSRAM/NOR read timings
multiplexed PSRAM/NOR write
Table 32: Asynchronous non-multiplexed SRAM/PSRAM/NOR write
timings
In
Table 38: Synchronous non-multiplexed PSRAM write
– t
– t
– t
Figure 28: Synchronous multiplexed NOR/PSRAM read
Figure 29: Synchronous multiplexed PSRAM write timings
Figure 31: Synchronous non-multiplexed PSRAM write timings
modified.
Figure 52: I2S slave timing diagram (Philips protocol)(1)
I2S master timing diagram (Philips protocol)(1)
WLCSP64 package added (see
STM32F103xE performance line WLCSP64 ballout, ball
High-density STM32F103xx pin
4.466 × 4.395 mm, 0.500 mm pitch, wafer-level chip-scale package
outline
pitch, wafer-level chip-scale package mechanical
Small text changes.
w(NADV)
updated
column to Remap column
Table 5: High-density STM32F103xx pin
Table 36: Synchronous multiplexed PSRAM write timings
v(Data-CLK)
d(CLKL-Data)
h(CLKL-DV)
Doc ID 14611 Rev 8
17,
and
values modified in
Figure 18
Table 68: WLCSP, 64-ball 4.466 × 4.395 mm, 0.500 mm
/ t
renamed as t
min value removed and max value added
h(CLKL-ADV)
Table 14: Maximum current consumption in Run mode,
Table 25: HSI oscillator
and
Figure 24: Asynchronous non-multiplexed
on page
on page
Figure 19
removed
d(CLKL-Data)
Table 31: Asynchronous non-multiplexed
Changes
timings. t
Figure 8: STM32F103xC and
definitions,
Asynchronous waveforms and
1.
Table 6: FSMC pin
1.
and
Figure 4: STM32F103xC and
modified.
show typical curves (titles
and
Table 34: Asynchronous
h(Data_NWE)
characteristics.
Figure 25: Asynchronous
definitions:
waveforms.
Figure 65: WLCSP, 64-ball
modified. ACC
and
modified.
data).
corrected.
Table 16: Maximum
definition.
Revision history
modified in
timings:
timings,
and
and
side,
and
and
Figure 53:
HSI
Table 22:
Table 5:
timings.
127/130
max
RAM.