STM32F103ZC STMicroelectronics, STM32F103ZC Datasheet - Page 128

• Manufacturer Part Number: STM32F103ZC
• Description: Mainstream Performance line, ARM Cortex-M3 MCU with 256 Kbytes Flash, 72 MHz CPU, motor control, USB and CAN
• Manufacturer: STMicroelectronics

Specifications of STM32F103ZC

• Core: ARM 32-bit Cortex™-M3 CPU
• Conversion Range: 0 to 3.6 V
• Dma: 12-channel DMA controller
• Supported Peripherals: timers, ADCs, DAC, SDIO, I2Ss, SPIs, I2Cs and USARTs
• Systick Timer: a 24-bit downcounter

Revision history
128/130
Table 75.
24-Sep-2009
21-Jul-2009
Date
Document revision history
Revision
6
7
Figure 1: STM32F103xC, STM32F103xD and STM32F103xE
performance line block diagram
Note 5
STM32F103xx pin
V
voltage.
Table 16: Maximum current consumption in Sleep mode, code running
from Flash or RAM
f
characteristics.
C
characteristics
32.768
Note 1
crystal.
removed from
Jitter added to
Figure 47: Recommended NRST pin protection
In
timings: t
In
timings: t
In
t
In
t
In
t
In
cycles: t
Table 53: SPI characteristics
characteristics
C
R
Table 63: DAC characteristics
buffered DAC
Figure 64: LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array
package outline
pitch ball grid array package mechanical data
Number of DACs corrected in
I
consumptions in Stop and Standby
Figure 16: Typical current consumption on VBAT with RTC on vs.
temperature at different VBAT values
IEC 1000 standard updated to IEC 61000 and SAE J1752/3 updated to
IEC 61967-2 in
Table 63: DAC characteristics
HSE_ext
h(AD_NADV)
h(A_NWE)
h(CLKH-NWAITV)
DD_VBAT
RERINT
L1
ADC
AIN
Table 31: Asynchronous non-multiplexed SRAM/PSRAM/NOR read
Table 32: Asynchronous non-multiplexed SRAM/PSRAM/NOR write
Table 33: Asynchronous multiplexed PSRAM/NOR read
Table 34: Asynchronous multiplexed PSRAM/NOR write
Table 35: Synchronous multiplexed NOR/PSRAM read
Table 40: Switching characteristics for NAND Flash read and write
and C
Doc ID 14611 Rev 8
max values modified in
and R
updated and
modified below
kHz), notes modified and moved below the tables.
Table 25: HSI oscillator characteristics
h(NOE-D)
min modified in
and T
h(BL_NOE)
h(A_NWE)
updated in
modified.
L2
and t
AIN
replaced by C in
added.
Table 27: Low-power mode wakeup
Coeff
Table 28: PLL
and
and
Section 5.3.11: EMC characteristics on page
modified.
parameters modified in
and
h(A_NOE)
modified.
STM32F103xC, STM32F103xD, STM32F103xE
and t
definitions.
and t
Table 24: LSE oscillator characteristics (fLSE =
Table 55: SD / MMC
added to
modified.
Note 4
Table 17: Typical and maximum current
Table 67: LFBGA100 - 10 x 10 mm low profile fine
Figure 22: Typical application with an 8 MHz
h(Data_NWE)
h(A_NOE)
Table 21: High-speed external user clock
modified.
added in
Table 60: RAIN max for fADC = 14
Table 13: Embedded internal reference
modified. Values added to
characteristics.
Table 23: HSE 4-16 MHz oscillator
Table 3: STM32F103xx
modified.
modified. Small text changes.
Changes
updated.
modified.
modified.
modes.
Table 5: High-density
added.
Table 59: ADC
Figure 61: 12-bit buffered /non-
characteristics.
updated.
modified. Conditions
modified.
timings.
family.
characteristics.
Table 54: I2S
timings:
timings:
timings:
83.
MHz.