STM32F103ZC STMicroelectronics, STM32F103ZC Datasheet - Page 35

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STM32F103ZC

Manufacturer Part Number
STM32F103ZC
Description
Mainstream Performance line, ARM Cortex-M3 MCU with 256 Kbytes Flash, 72 MHz CPU, motor control, USB and CAN
Manufacturer
STMicroelectronics
Datasheet

Specifications of STM32F103ZC

Core
ARM 32-bit Cortex™-M3 CPU
Conversion Range
0 to 3.6 V
Dma
12-channel DMA controller
Supported Peripherals
timers, ADCs, DAC, SDIO, I2Ss, SPIs, I2Cs and USARTs
Systick Timer
a 24-bit downcounter

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STM32F103xC, STM32F103xD, STM32F103xE
Table 5.
1. I = input, O = output, S = supply.
2. FT = 5 V tolerant.
3. Function availability depends on the chosen device.
4. If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should
5. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3
6. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even
7. Unlike in the LQFP64 package, there is no PC3 in the WLCSP package. The V
8. This alternate function can be remapped by software to some other port pins (if available on the used package). For more
9. For the LQFP64 package, the pins number 5 and 6 are configured as OSC_IN/OSC_OUT after reset, however the
10. For devices delivered in LQFP64 packages, the FSMC function is not available.
C6 B5 B5 58 92 136
D6 A5 C5 59 93 137
D5 D5 A6 60 94 138
C5 B4 D5 61 95 139
A7 A7 A4 55 89 133
A6 A6 B4 56 90 134
B6 C5 A5 57 91 135
B5 A4 B6 62 96 140
A5 D4
A4 C4
E5 E5 A7 63 99 143
F5
be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register).
mA), the use of GPIOs PC13 to PC15 in output mode is limited: the speed should not exceed 2 MHz with a maximum load
of 30 pF and these IOs must not be used as a current source (e.g. to drive an LED).
after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the
Battery backup domain and BKP register description sections in the STM32F10xxx reference manual, available from the
STMicroelectronics website: www.st.com.
details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual,
available from the STMicroelectronics website: www.st.com.
functionality of PD0 and PD1 can be remapped by software on these pins. For the LQFP100/BGA100 and
LQFP144/BGA144 packages, PD0 and PD1 are available by default, so there is no need for remapping. For more details,
refer to Alternate function I/O and debug configuration section in the STM32F10xxx reference manual.
F5 A8 64 100 144
Pins
-
-
High-density STM32F103xx pin definitions (continued)
-
-
97 141
98 142
Pin name
BOOT0
V
V
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PE0
PE1
DD_3
SS_3
I/O FT
I/O FT
I/O
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
S
S
I
Doc ID 14611 Rev 8
(after reset)
function
NJTRST
BOOT0
JTDO
V
V
Main
PB5
PB6
PB7
PB8
PB9
PE0
PE1
DD_3
SS_3
(3)
I2C1_SCL
TIM4_ETR / FSMC_NBL0
I2C1_SMBA/ SPI3_MOSI
TIM4_CH3
TIM4_CH4
SPI3_SCK / I2S3_CK/
REF+
FSMC_NADV /
I2C1_SDA
TIM4_CH2
FSMC_NBL1
SPI3_MISO
I2S3_SD
functionality is provided instead.
Default
(8)
Alternate functions
Pinouts and pin descriptions
/ TIM4_CH1
(8)
(8)
/SDIO_D4
/SDIO_D5
(8)
(8)
/
(8)
PB3/TRACESWO
PB4 / TIM3_CH1
USART1_RX
USART1_TX
TIM2_CH2 /
TIM3_CH2 /
SPI1_MISO
SPI1_MOSI
I2C1_SDA /
I2C1_SCL/
SPI1_SCK
(4)
CAN_RX
CAN_TX
Remap
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