STM32F103ZC STMicroelectronics, STM32F103ZC Datasheet - Page 65

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STM32F103ZC

Manufacturer Part Number
STM32F103ZC
Description
Mainstream Performance line, ARM Cortex-M3 MCU with 256 Kbytes Flash, 72 MHz CPU, motor control, USB and CAN
Manufacturer
STMicroelectronics
Datasheet

Specifications of STM32F103ZC

Core
ARM 32-bit Cortex™-M3 CPU
Conversion Range
0 to 3.6 V
Dma
12-channel DMA controller
Supported Peripherals
timers, ADCs, DAC, SDIO, I2Ss, SPIs, I2Cs and USARTs
Systick Timer
a 24-bit downcounter

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STM32F103xC, STM32F103xD, STM32F103xE
Table 31.
1. C
2. Based on characterisation, not tested in production.
Figure 25. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms
1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used.
Table 32.
t
t
t
t
t
t
t
t
t
t
t
t
v(NADV_NE)
w(NADV)
w(NE)
v(NWE_NE)
w(NWE)
h(NE_NWE)
v(A_NE)
h(A_NWE)
v(BL_NE)
h(BL_NWE)
v(Data_NE)
h(Data_NWE)
Symbol
Symbol
L
= 15 pF.
FSMC_NBL[1:0]
FSMC_NADV
FSMC_A[25:0]
FSMC_D[15:0]
FSMC_NWE
FSMC_NOE
FSMC_NEx
Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings
Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings
FSMC_NEx low to FSMC_NADV low
FSMC_NADV low time
FSMC_NE low time
FSMC_NEx low to FSMC_NWE low
FSMC_NWE low time
FSMC_NWE high to FSMC_NE high hold time
FSMC_NEx low to FSMC_A valid
Address hold time after FSMC_NWE high
FSMC_NEx low to FSMC_BL valid
FSMC_BL hold time after FSMC_NWE high
FSMC_NEx low to Data valid
Data hold time after FSMC_NWE high
(1)
Parameter
Parameter
Doc ID 14611 Rev 8
t
t
v(NADV_NE)
v(NWE_NE)
t
v(A_NE)
t
t
t
v(BL_NE)
w(NADV)
v(Data_NE)
Address
t
w(NE)
NBL
t
w(NWE)
t
h(Data_NWE)
t
h(BL_NWE)
t
h(A_NWE)
Data
t
3t
t
t
t
t
t
HCLK
HCLK
HCLK
HCLK
HCLK
HCLK
HCLK
Min
Min
– 0.5
– 0.5
– 0.5
– 1
Electrical characteristics
t
t
5
HCLK
h(NE_NWE)
3t
t
t
t
7.5
1.5
HCLK
HCLK
HCLK
HCLK
Max
Max
+ 1.5
+ 1.5
+ 1.5
+ 7
+ 2
ai14990
(1) (2)
(1)(2)
ns
ns
65/130
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
Unit

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