STM32F103ZC STMicroelectronics, STM32F103ZC Datasheet - Page 68

• Manufacturer Part Number: STM32F103ZC
• Description: Mainstream Performance line, ARM Cortex-M3 MCU with 256 Kbytes Flash, 72 MHz CPU, motor control, USB and CAN
• Manufacturer: STMicroelectronics

Specifications of STM32F103ZC

• Core: ARM 32-bit Cortex™-M3 CPU
• Conversion Range: 0 to 3.6 V
• Dma: 12-channel DMA controller
• Supported Peripherals: timers, ADCs, DAC, SDIO, I2Ss, SPIs, I2Cs and USARTs
• Systick Timer: a 24-bit downcounter

Electrical characteristics
68/130
Figure 27. Asynchronous multiplexed PSRAM/NOR write waveforms
Table 34.
1. C
2. Based on characterization, not tested in production.
t
t
t
t
t
t
t
t
t
t
t
t
t
w(NE)
v(NWE_NE)
w(NWE)
h(NE_NWE)
v(A_NE)
v(NADV_NE)
w(NADV)
h(AD_NADV)
h(A_NWE)
v(BL_NE)
h(BL_NWE)
v(Data_NADV)
h(Data_NWE)
Symbol
L
= 15 pF.
FSMC_NBL[1:0]
FSMC_ AD[15:0]
FSMC_A[25:16]
FSMC_NADV
FSMC_NWE
FSMC_NOE
FSMC_NEx
Asynchronous multiplexed PSRAM/NOR write timings
FSMC_NE low time
FSMC_NEx low to FSMC_NWE low
FSMC_NWE low time
FSMC_NWE high to FSMC_NE high hold time
FSMC_NEx low to FSMC_A valid
FSMC_NEx low to FSMC_NADV low
FSMC_NADV low time
FSMC_AD (address) valid hold time after
FSMC_NADV high
Address hold time after FSMC_NWE high
FSMC_NEx low to FSMC_BL valid
FSMC_BL hold time after FSMC_NWE high
FSMC_NADV high to Data valid
Data hold time after FSMC_NWE high
Doc ID 14611 Rev 8
Parameter
t
v(NADV_NE)
t
t
t
v(A_NE)
v(A_NE)
t
t
v(NWE_NE)
v(BL_NE)
w(NADV)
Address
STM32F103xC, STM32F103xD, STM32F103xE
Address
t
t
t
v(Data_NADV)
w(NE)
h(AD_NADV)
NBL
t
w(NWE)
t
h(BL_NWE)
t
h(A_NWE)
Data
5t
2t
2t
t
3
t
t
4t
t
t
HCLK
HCLK
HCLK
HCLK
HCLK
HCLK
HCLK
HCLK
HCLK
Min
– 1
– 1
– 3
– 1.5
– 5
– 1
– 1
(1)(2)
t
5t
2t
2t
7
5
t
1.6
t
h(Data_NWE)
HCLK
HCLK
t
h(NE_NWE)
HCLK
HCLK
HCLK
Max
+ 1
+ 1.5
+ 2
+ 1
+ 2
ai14891B
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit