STM32F101RG STMicroelectronics, STM32F101RG Datasheet - Page 30

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STM32F101RG

Manufacturer Part Number
STM32F101RG
Description
Mainstream Access line, ARM Cortex-M3 MCU with 1 Mbyte Flash, 36 MHz CPU
Manufacturer
STMicroelectronics
Datasheet

Specifications of STM32F101RG

Conversion Range
0 to 3.6 V
Peripherals Supported
timers, ADC, DAC, SPIs, I2Cs and USARTs
Systick Timer
a 24-bit downcounter

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Pinouts and pin descriptions
Table 5.
1. I = input, O = output, S = supply.
2. FT = 5 V tolerant.
3. Function availability depends on the chosen device.
4. If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should
5. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current
6. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even
7. This alternate function can be remapped by software to some other port pins (if available on the used package). For more
8. For the LQFP64 package, the pins number 5 and 6 are configured as OSC_IN/OSC_OUT after reset, however the
9. For devices delivered in LQFP64 packages, the FSMC function is not available.
30/108
133 55 89
134 56 90
135 57 91
136 58 92
137 59 93
138 60 94
139 61 95
140 62 96
141
142
143 63 99
144 64 100
be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register).
(3 mA), the use of GPIOs PC13 to PC15 in output mode is limited: the speed should not exceed 2 MHz with a maximum
load of 30 pF and these IOs must not be used as a current source (e.g. to drive an LED).
after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the
Battery backup domain and BKP register description sections in the STM32F10xxx reference manual, available from the
STMicroelectronics website: www.st.com.
details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual,
available from the STMicroelectronics website: www.st.com.
functionality of PD0 and PD1 can be remapped by software on these pins. For the LQFP100 and LQFP144 packages, PD0
and PD1 are available by default, so there is no need for remapping. For more details, refer to Alternate function I/O and
debug configuration section in the STM32F10xxx reference manual
Pins
-
-
97
98
STM32F101xF and STM32F101xG pin definitions (continued)
Pin name
BOOT0
V
V
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PE0
PE1
DD_3
SS_3
I/O FT
I/O FT
I/O
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
S
S
I
Doc ID 17143 Rev 2
(after reset)
function
NJTRST
BOOT0
V
JTDO
V
Main
PB5
PB6
PB7
PB8
PB9
PE0
PE1
DD_3
SS_3
(3)
TIM4_ETR
I2C1_SDA / FSMC_NADV /
I2C1_SMBA/ SPI3_MOSI
I2C1_SCL / TIM4_CH1
TIM4_CH3
TIM4_CH4
FSMC_NBL1
TIM4_CH2
SPI3_MISO
SPI3_SCK
Default
(7)
Alternate functions
/ FSMC_NBL0
STM32F101xF, STM32F101xG
(7)
(7)
(7)
(7)
PB4 / TIM3_CH1
TIM2_CH2 /PB3
USART1_RX
TRACESWO
USART1_TX
TIM3_CH2 /
SPI1_MISO
SPI1_MOSI
(4)
SPI1_SCK
I2C1_SDA
I2C1_SCL
Remap

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