STM32F103VF STMicroelectronics, STM32F103VF Datasheet - Page 23

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STM32F103VF

Manufacturer Part Number
STM32F103VF
Description
Mainstream Performance line, ARM Cortex-M3 MCU with 768 Kbytes Flash, 72MHz CPU, motor control, USB and CAN
Manufacturer
STMicroelectronics
Datasheet

Specifications of STM32F103VF

Conversion Range
0 to 3.6 V
Supported Peripherals
timers, ADCs, DAC, SDIO, I2Ss, SPIs, I2Cs and USARTs
Systick Timer
a 24-bit downcounter

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STM32F103xF, STM32F103xG
2.3.27
2.3.28
The I/Os alternate function configuration can be locked if needed following a specific
sequence in order to avoid spurious writing to the I/Os registers.
ADC (analog to digital converter)
Three 12-bit analog-to-digital converters are embedded into STM32F103xF and
STM32F103xG performance line devices and each ADC shares up to 21 external channels,
performing conversions in single-shot or scan modes. In scan mode, automatic conversion
is performed on a selected group of analog inputs.
Additional logic functions embedded in the ADC interface allow:
The ADC can be served by the DMA controller.
An analog watchdog feature allows very precise monitoring of the converted voltage of one,
some or all selected channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
The events generated by the general-purpose timers (TIMx) and the advanced-control
timers (TIM1 and TIM8) can be internally connected to the ADC start trigger and injection
trigger, respectively, to allow the application to synchronize A/D conversion and timers.
DAC (digital-to-analog converter)
The two 12-bit buffered DAC channels can be used to convert two digital signals into two
analog voltage signal outputs. The chosen design structure is composed of integrated
resistor strings and an amplifier in inverting configuration.
This dual digital Interface supports the following features:
Eight DAC trigger inputs are used in the STM32F103xF and STM32F103xG performance
line family. The DAC channels are triggered through the timer update outputs that are also
connected to different DMA channels.
Simultaneous sample and hold
Interleaved sample and hold
Single shunt
two DAC converters: one for each output channel
8-bit or 12-bit monotonic output
left or right data alignment in 12-bit mode
synchronized update capability
noise-wave generation
triangular-wave generation
dual DAC channel independent or simultaneous conversions
DMA capability for each channel
external triggers for conversion
input voltage reference V
REF+
Doc ID 16554 Rev 3
Description
23/120

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