STM32F103R4 STMicroelectronics, STM32F103R4 Datasheet - Page 27

• Manufacturer Part Number: STM32F103R4
• Description: Mainstream Performance line, ARM Cortex-M3 MCU with 16 Kbytes Flash, 72 MHz CPU, motor control, USB and CAN
• Manufacturer: STMicroelectronics

Specifications of STM32F103R4

• Conversion Range: 0 to 3.6 V
• Peripherals Supported: timers, ADC, SPIs, I2Cs and USARTs

STM32F103x4, STM32F103x6
Table 5.
1. I = input, O = output, S = supply.
2. FT = 5 V tolerant.
3. Function availability depends on the chosen device. For devices having reduced peripheral counts, it is always the lower
4. If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should
5. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current
6. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even
7. Unlike in the LQFP64 package, there is no PC3 in the TFBGA64 package. The V
8. This alternate function can be remapped by software to some other port pins (if available on the used package). For more
9. The pins number 2 and 3 in the VFQFPN36 package, 5 and 6 in the LQFP48 and LQFP64 packages and C1 and C2 in the
39
40
41
42
43
44
45
46
47
48
5
6
number of peripheral that is included. For example, if a device has only one SPI and two USARTs, they will be called SPI1
and USART1 & USART2, respectively. Refer to
be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register).
(3 mA), the use of GPIOs PC13 to PC15 in output mode is limited: the speed should not exceed 2 MHz with a maximum
load of 30 pF and these IOs must not be used as a current source (e.g. to drive an LED).
after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the
Battery backup domain and BKP register description sections in the STM32F10xxx reference manual, available from the
STMicroelectronics website: www.st.com.
details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual, available
from the STMicroelectronics website: www.st.com.
TFBGA64 package are configured as OSC_IN/OSC_OUT after reset, however the functionality of PD0 and PD1 can be
remapped by software on these pins. For more details, refer to the Alternate function I/O and debug configuration section in
the STM32F10xxx reference manual.
54
55
56
57
58
59
60
61
62
63
64
5
6
Pins
C1
D1
C4
D3
C3
D4
B5
A5
A4
B4
B3
A3
E4
Low-density STM32F103xx pin definitions (continued)
30
31
32
33
34
35
36
2
3
1
-
-
-
Pin name
BOOT0
V
V
PD0
PD1
PD2
PB3
PB4
PB5
PB6
PB7
PB8
PB9
DD_3
SS_3
I/O FT
I/O FT OSC_OUT
I/O FT
I/O FT
I/O FT
I/O
I/O FT
I/O FT
I/O FT
I/O FT
S
S
Table 2 on page
I
Doc ID 15060 Rev 5
(after reset)
function
OSC_IN
NJTRST
BOOT0
JTDO
V
V
Main
PD2
PB5
PB6
PB7
PB8
PB9
DD_3
SS_3
10.
(9)
(3)
(9)
REF+
I2C1_SCL
I2C1_SDA
I2C1_SMBA
TIM3_ETR
Default
functionality is provided instead.
Alternate functions
Pinouts and pin description
(8)
(8)
/
TIM2_CH2 / PB3/
TIM3_CH1 /PB4
USART1_TX
USART1_RX
TRACESWO
SPI1_MISO
TIM3_CH2 /
SPI1_MOSI
I2C1_SDA /
(4)
SPI1_SCK
I2C1_SCL
/CAN_RX
CAN_TX
Remap
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