STM32F102RB STMicroelectronics, STM32F102RB Datasheet - Page 11

• Manufacturer Part Number: STM32F102RB
• Description: Mainstream USB Access line, ARM Cortex-M3 MCU with 128 Kbytes Flash, 48 MHz CPU, USB FS
• Manufacturer: STMicroelectronics

Specifications of STM32F102RB

• Core: ARM 32-bit Cortex™-M3 CPU
• Peripherals Supported: timers, ADC, SPIs, I2Cs and USARTs
• Conversion Range: 0 to 3.6 V
• Systick Timer: 24-bit downcounter

STM32F102x8, STM32F102xB
Figure 2.
1. For the USB function to be available, both HSE and PLL must be enabled, with the CPU running at
2. To have an ADC conversion time of 1.2 µs, APB2 must be at 12 MHz, 24 MHz or 48 MHz.
OSC32_OUT
48 MHz.
OSC32_IN
OSC_OUT
OSC_IN
MCO
Clock tree
4-16 MHz
32.768 kHz
HSE OSC
Main
Clock Output
LSE OSC
HSI RC
8 MHz
LSI RC
40 kHz
PLLSRC
MCO
x2, x3, x4
PLLMUL
HSI
..., x16
PLLXTPRE
PLL
/2
/128
LSE
LSI
/2
RTCSEL[1:0]
/2
Doc ID 15056 Rev 3
HSE
PLLCLK
SYSCLK
HSI
PLLCLK
RTCCLK
to Independent Watchdog (IWDG)
HSI
HSE
CSS
SW
SYSCLK
48 MHz
to RTC
max
IWDGCLK
Prescaler
/1, 2..512
AHB
Prescaler
/1, 1.5
USB
/1, 2, 4, 8, 16
/1, 2, 4, 8, 16
TIM2,3, 4
If (APB1 prescaler =1) x1
else
/8
Prescaler
Prescaler
48 MHz max
APB1
APB2
Clock
Enable (3 bits)
48 MHz
Legend:
HSE = high-speed external clock signal
HSI = high-speed internal clock signal
LSI = low-speed internal clock signal
LSE = low-speed external clock signal
48 MHz max
24 MHz max
Peripheral Clock
Peripheral Clock
Enable (13 bits)
Enable (11 bits)
Prescaler
/2, 4, 6, 8
USBCLK
to USB interface
x2
ADC
HCLK
to AHB bus, core,
memory and DMA
FCLK Cortex
free running clock
to Cortex System timer
Peripheral Clock
Enable (3 bits)
Description
TIMXCLK
PCLK1
PCLK2
to APB1
peripherals
to APB2
peripherals
ADCCLK
to TIM2, 3
and 4
ai14994
to ADC
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