STM32F102RB STMicroelectronics, STM32F102RB Datasheet - Page 21

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STM32F102RB

Manufacturer Part Number
STM32F102RB
Description
Mainstream USB Access line, ARM Cortex-M3 MCU with 128 Kbytes Flash, 48 MHz CPU, USB FS
Manufacturer
STMicroelectronics
Datasheet

Specifications of STM32F102RB

Core
ARM 32-bit Cortex™-M3 CPU
Peripherals Supported
timers, ADC, SPIs, I2Cs and USARTs
Conversion Range
0 to 3.6 V
Systick Timer
24-bit downcounter

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Table 4.
1. I = input, O = output, S = supply.
2. FT= 5 V tolerant.
3. Function availability depends on the chosen device. For devices having reduced peripheral counts, it is always the lower
4. If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should
5. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3
6. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even
7. The pins number 5 and 6 in the LQFP48 package are configured as OSC_IN/OSC_OUT after reset, however the
8. This alternate function can be remapped by software to some other port pins (if available on the used package). For more
41
42
43
44
45
46
47
48
number of peripherals that is included. For example, if a device has only one SPI, two USARTs and two timers, they will be
called SPI1, USART1 & USART2 and TIM2 & TIM 3, respectively. Refer to
be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register).
mA), the use of GPIOs PC13 to PC15 in output mode is limited: the speed should not exceed 2 MHz with a maximum load
of 30 pF and these IOs must not be used as a current source (e.g. to drive an LED).
after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the
Battery backup domain and BKP register description sections in the STM32F102xx reference manual, available from the
STMicroelectronics website: www.st.com.
functionality of PD0 and PD1 can be remapped by software on these pins. For more details, refer to the Alternate function
I/O and debug configuration section in the STM32F10xxx reference manual.
The use of PD0 and PD1 in output mode is limited as they can only be used at 50 MHz in output mode.
details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual,
available from the STMicroelectronics website: www.st.com.
Pins
57
58
59
60
61
62
63
64
Medium-density STM32F102xx pin definitions (continued)
Pin name
BOOT0
V
V
PB5
PB6
PB7
PB8
PB9
DD_3
SS_3
I/O
I/O
I/O
I/O
I/O
S
S
I
FT
FT
FT
FT
Doc ID 15056 Rev 3
(after reset)
function
BOOT0
V
V
Main
PB5
PB6
PB7
PB8
PB9
DD_3
SS_3
(3)
I2C1_SCL
I2C1_SDA
Table 2 on page 9Table 3 on page
I2C1_SMBA
TIM4_CH3
TIM4_CH4
Default
Alternate functions
(8)
(8)
Pinouts and pin description
/ TIM4_CH1
/ TIM4_CH2
(3) (4)
USART1_RX
USART1_TX
TIM3_CH2 /
SPI1_MOSI
I2C1_SCL
I2C1_SDA
12.
Remap
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