STM32F417IE STMicroelectronics, STM32F417IE Datasheet - Page 115

• Manufacturer Part Number: STM32F417IE
• Description: High-performance and DSP with FPU, ARM Cortex-M4 MCU with 512 Kbytes Flash, 168 MHz CPU, Art Accelerator, Ethernet, HW crypto
• Manufacturer: STMicroelectronics

Specifications of STM32F417IE

• Core: ARM 32-bit Cortex™-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait state execution from Flash memory, frequency up to 168 MHz, memory protection unit, 210 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions
• 3×12-bit, 2.4 Msps A/d Converters: up to 24 channels and 7.2 MSPS in triple interleaved mode
• General-purpose Dma: 16-stream DMA controller with FIFOs and burst support
• Up To 17 Timers: up to twelve 16-bit and two 32-bit timers up to 168 MHz, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input
• 10/100 Ethernet Mac With Dedicated Dma: supports IEEE 1588v2 hardware, MII/RMII
• Cryptographic Acceleration: hardware acceleration for AES 128, 192, 256, Triple DES, HASH (MD5, SHA-1), and HMAC
• Rtc: subsecond accuracy, hardware calendar

STM32F415xx, STM32F417xx
Figure 42. USB OTG FS timings: definition of data signal rise and fall time
Table 56.
1. Guaranteed by design, not tested in production.
2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB
Table 57.
1. Guaranteed by design, not tested in production.
2. TBD stands for “to be defined”.
f
USB FS interface
Frequency (first transition)
Frequency (steady state) ±500 ppm
Duty cycle (first transition)
Duty cycle (steady state) ±500 ppm
Time to reach the steady state frequency and
duty cycle after the first transition
Clock startup time after the
de-assertion of SuspendM
PHY preparation time after the first transition
of the input clock
HCLK
Symbol
V
Specification - Chapter 7 (version 2.0).
t
CRS
rfm
t
t
r
f
value to guarantee proper operation of
data lines
Differen tial
Rise time
Fall time
Rise/ fall time matching
Output signal crossover voltage
USB OTG FS electrical characteristics
USB FS clock timing parameters
V CRS
Parameter
V S S
(2)
(2)
Parameter
t f
8-bit ±10%
8-bit ±10%
Peripheral
Host
Doc ID 022063 Rev 2
Crossover
points
Driver characteristics
t r
F
F
D
D
T
T
T
T
START_8BIT
STEADY
STEADY
START_DEV
START_HOST
PREP
START_8BIT
STEADY
Symbol
Conditions
C
C
L
L
(1)(2)
-
= 50 pF
= 50 pF
(1)
t
r
/t
f
14.2
TBD
TBD
TBD
TBD
Min
-
-
-
-
Min
1.3
90
4
4
Electrical characteristics
Nominal
TBD
TBD
TBD
TBD
-
-
-
-
Max
110
2.0
20
20
TBD
TBD
TBD
TBD
TBD
TBD
Max
ai14137
-
-
Unit
115/168
ns
ns
%
V
MHz
MHz
MHz
Unit
ms
ms
µs
%
%