STM32F417IE STMicroelectronics, STM32F417IE Datasheet - Page 119

• Manufacturer Part Number: STM32F417IE
• Description: High-performance and DSP with FPU, ARM Cortex-M4 MCU with 512 Kbytes Flash, 168 MHz CPU, Art Accelerator, Ethernet, HW crypto
• Manufacturer: STMicroelectronics

Specifications of STM32F417IE

• Core: ARM 32-bit Cortex™-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait state execution from Flash memory, frequency up to 168 MHz, memory protection unit, 210 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions
• 3×12-bit, 2.4 Msps A/d Converters: up to 24 channels and 7.2 MSPS in triple interleaved mode
• General-purpose Dma: 16-stream DMA controller with FIFOs and burst support
• Up To 17 Timers: up to twelve 16-bit and two 32-bit timers up to 168 MHz, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input
• 10/100 Ethernet Mac With Dedicated Dma: supports IEEE 1588v2 hardware, MII/RMII
• Cryptographic Acceleration: hardware acceleration for AES 128, 192, 256, Triple DES, HASH (MD5, SHA-1), and HMAC
• Rtc: subsecond accuracy, hardware calendar

STM32F415xx, STM32F417xx
5.3.20
Table 65.
R
Symbol
C
f
R
ADC
V
TRIG
V
t
t
f
V
ADC
latr
AIN
lat
REF+
ADC
DDA
AIN
(5)
(5)(7)
(5)
(5)
(5)
(5)
Power supply
Positive reference voltage
ADC clock frequency
External trigger frequency
Conversion voltage range
External input impedance
Sampling switch resistance
Internal sample and hold
capacitor
Injection trigger conversion
latency
Regular trigger conversion
latency
Table 64.
1. TBD stands for “to be defined”.
CAN (controller area network) interface
Refer to
function characteristics (CANTX and CANRX).
12-bit ADC characteristics
Unless otherwise specified, the parameters given in
performed under the ambient temperature, f
conditions summarized in
ADC characteristics
Symbol
t
t
t
su(RXD)
d(TXEN)
t
t
t
ih(RXD)
t
t
su(ER)
d(TXD)
su(DV)
ih(ER)
ih(DV)
Parameter
Section 5.3.16: I/O port characteristics
Dynamics characteristics: Ethernet MAC signals for MII
Receive data setup time
Receive data hold time
Data valid setup time
Data valid hold time
Error setup time
Error hold time
Transmit enable valid delay time
Transmit data valid delay time
(6)
(1)
Table
V
V
Rating
DDA
Doc ID 022063 Rev 2
DDA
See
f
f
f
11.
ADC
ADC
ADC
= 1.8
Conditions
= 2.4 to 3.6 V
Equation 1
details
= 30 MHz
= 30 MHz
= 30 MHz
(2)(4)
to 2.4 V
PCLK2
for
(4)
for more details on the input/output alternate
frequency and V
0 (V
tied to ground)
Table 65
TBD
TBD
TBD
TBD
TBD
TBD
13.4
12.9
Min
1.8
SSA
1.8
Min
(2)(3)(4)
0.6
0.6
-
-
or V
-
-
-
-
-
-
-
(2)
REF-
are derived from tests
TBD
TBD
TBD
TBD
TBD
TBD
15.5
16.1
Typ
Electrical characteristics
DDA
Typ
15
30
4
-
-
-
-
-
-
-
-
-
-
-
supply voltage
(1)
Max
TBD
TBD
TBD
TBD
TBD
TBD
17.7
19.4
V
0.100
0.067
V
TBD
Max
3
2
3.6
REF+
18
36
17
50
DDA
6
-
(8)
(8)
119/168
1/f
1/f
1/f
Unit
MHz
MHz
Unit
kHz
ns
ns
ns
ns
ns
ns
ns
ns
kΩ
kΩ
pF
µs
µs
V
V
V
ADC
ADC
ADC