STM32F417IE STMicroelectronics, STM32F417IE Datasheet - Page 120

• Manufacturer Part Number: STM32F417IE
• Description: High-performance and DSP with FPU, ARM Cortex-M4 MCU with 512 Kbytes Flash, 168 MHz CPU, Art Accelerator, Ethernet, HW crypto
• Manufacturer: STMicroelectronics

Specifications of STM32F417IE

• Core: ARM 32-bit Cortex™-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait state execution from Flash memory, frequency up to 168 MHz, memory protection unit, 210 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions
• 3×12-bit, 2.4 Msps A/d Converters: up to 24 channels and 7.2 MSPS in triple interleaved mode
• General-purpose Dma: 16-stream DMA controller with FIFOs and burst support
• Up To 17 Timers: up to twelve 16-bit and two 32-bit timers up to 168 MHz, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input
• 10/100 Ethernet Mac With Dedicated Dma: supports IEEE 1588v2 hardware, MII/RMII
• Cryptographic Acceleration: hardware acceleration for AES 128, 192, 256, Triple DES, HASH (MD5, SHA-1), and HMAC
• Rtc: subsecond accuracy, hardware calendar

Electrical characteristics
Table 65.
1. TBD stands for “to be defined”.
2. If an inverted reset signal is applied to PDR_ON, this value can be lowered to 1.7 V when the device operates in a reduced
3. It is recommended to maintain the voltage difference between V
4. V
5. Based on characterization, not tested in production.
6. V
7. R
8. For external triggers, a delay of 1/f
120/168
I
I
VREF+
DDA
Symbol
t
t
CONV
STAB
temperature range (0 to 70 °C).
t
f
S
S
DDA
REF+
ADC
(5)
(5)
(5)
(5)
(5)
(5)
-V
maximum value is given for V
is internally connected to V
REF+
Sampling time
Power-up time
Total conversion time (including
sampling time)
Sampling rate
(f
t
ADC V
consumption in conversion
mode
ADC V
consumption in conversion
mode
S
ADC
ADC characteristics
= 3 ADC cycles)
< 1.2 V.
= 30 MHz, and
REF
DDA
Parameter
DC current
DC current
DDA
PCLK2
DD
=1.8 V, and minimum value for V
and V
(1)
must be added to the latency specified in
(continued)
REF-
9 to 492 (t
approximation)
Interleave Triple ADC
Interleave Dual ADC
is internally connected to V
Doc ID 022063 Rev 2
480 sampling time
480 sampling time
12-bit resolution
10-bit resolution
12-bit resolution
12-bit resolution
12-bit resolution
12-bit resolution
12-bit resolution
12-bit resolution
12-bit resolution
3 sampling time
3 sampling time
f
f
f
f
8-bit resolution
f
6-bit resolution
f
f
f
f
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
Single ADC
Conditions
mode
mode
= 30 MHz
= 30 MHz
= 30 MHz
= 30 MHz
= 30 MHz
= 30 MHz
= 30 MHz
= 30 MHz
= 30 MHz
S
for sampling +n-bit resolution for successive
REF+
and V
DD
=3.3 V.
DDA
SSA
below 1.8 V.
.
0.100
0.416
0.360
0.305
0.250
Min
Table
3
-
-
-
-
-
-
-
-
STM32F415xx, STM32F417xx
65.
Typ
300
1.6
2
-
-
-
-
-
-
-
-
-
-
-
12.95
12.89
12.84
12.79
TBD
TBD
Max
3.75
416
500
1.8
16
3
2
6
1/f
1/f
Msps
Msps
Msps
Unit
mA
µA
µA
µs
µs
µs
µs
µs
µs
ADC
ADC