STM32F417IE STMicroelectronics, STM32F417IE Datasheet - Page 165

• Manufacturer Part Number: STM32F417IE
• Description: High-performance and DSP with FPU, ARM Cortex-M4 MCU with 512 Kbytes Flash, 168 MHz CPU, Art Accelerator, Ethernet, HW crypto
• Manufacturer: STMicroelectronics

Specifications of STM32F417IE

• Core: ARM 32-bit Cortex™-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait state execution from Flash memory, frequency up to 168 MHz, memory protection unit, 210 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions
• 3×12-bit, 2.4 Msps A/d Converters: up to 24 channels and 7.2 MSPS in triple interleaved mode
• General-purpose Dma: 16-stream DMA controller with FIFOs and burst support
• Up To 17 Timers: up to twelve 16-bit and two 32-bit timers up to 168 MHz, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input
• 10/100 Ethernet Mac With Dedicated Dma: supports IEEE 1588v2 hardware, MII/RMII
• Cryptographic Acceleration: hardware acceleration for AES 128, 192, 256, Triple DES, HASH (MD5, SHA-1), and HMAC
• Rtc: subsecond accuracy, hardware calendar

STM32F415xx, STM32F417xx
8
Revision history
Table 94.
15-Sep-2011
24-Jan-2012
Date
Document revision history
Revision
1
2
Initial release.
Added WLCSP90 package on cover page.
Renamed USART4 and USART5 into UART4 and UART5, respectively.
Updated number of USB OTG HS and FS in
and STM32F417xx: features and peripheral
Updated
STM32F10xx/STM32F2xx/STM32F4xx for LQFP144 package
Figure 4: Compatible board design between STM32F2xx and
STM32F4xx for LQFP176
Updated
Modified I/Os used to
USB OTG FS in
Updated note in
PDR_ON no more available on LQFP100 package. Updated
Section 2.2.16: Voltage
minimum supply voltage of 1.7 V in the whole document.
Renamed USART4/5 to UART4/5 and added LIN and IrDA feature for
UART4 and UART5 in
Removed support of I2C for OTG PHY in
serial bus on-the-go full-speed
Added
Table 6: STM32F41x pin and ball
and V
definitions
versus additional functions; signal corresponding to LQFP100 pin 99
changed from PDR_ON to V
alternate functions for all I/Os; ADC3_IN8 added as alternate function
for PF10; FSMC_CLE and FSMC_ALE added as alternate functions for
PD11 and PD12, respectively; PH10 alternate function
TIM15_CH1_ETR renamed TIM5_CH1; updated PA4 and PAA5 pin
type.
Removed OTG_HS_SCL, OTG_HS_SDA, OTG_FS_INTN,
OTG_FS_SDA, OTG_FS_SCL alternate functions in
STM32F41x pin and ball definitions
mapping.
Changed TCM data RAM to CCM data RAM in
map.
Added I
characteristics.
Added
operating
Updated
supply
Doc ID 022063 Rev 2
SS
Table 5: Legend/abbreviations used in the pinout
Note 1
range.
VDD
_8 by V
Figure 3: Compatible board design between
Section 2.2.9: Flexible static memory controller
Table 12: Limitations depending on the operating power
conditions, and added maximum power dissipation values.
to better highlight I/O structure, and alternate functions
and I
related to f
SS
Section 2.2.13: Boot
Section 2.2.14: Power supply
VSS
; reformatted
maximum values in
reprogram the Flash memory for
Table 4: USART feature
regulator. Updated condition to obtain a
HCLK
package, and removed note 1 and 2.
SS
, updated
Changes
; EVENTOUT added in the list of
(OTG_FS).
Table 6: STM32F41x pin and ball
definitions: replaced V
and
modes.
Note 2
Table 7: Alternate function
Table 9: Current
Section 2.2.29: Universal
counts.
Table 2: STM32F415xx
schemes.
comparison.
Figure 15: Memory
in
Table 11: General
Revision history
Table 6:
SS
table.
(FSMC).
_3, V
CAN2 and
and
165/168
SS
_4,