STM32F417IE STMicroelectronics, STM32F417IE Datasheet - Page 22

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STM32F417IE

Manufacturer Part Number
STM32F417IE
Description
High-performance and DSP with FPU, ARM Cortex-M4 MCU with 512 Kbytes Flash, 168 MHz CPU, Art Accelerator, Ethernet, HW crypto
Manufacturer
STMicroelectronics
Datasheet

Specifications of STM32F417IE

Core
ARM 32-bit Cortex™-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait state execution from Flash memory, frequency up to 168 MHz, memory protection unit, 210 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions
3×12-bit, 2.4 Msps A/d Converters
up to 24 channels and 7.2 MSPS in triple interleaved mode
General-purpose Dma
16-stream DMA controller with FIFOs and burst support
Up To 17 Timers
up to twelve 16-bit and two 32-bit timers up to 168 MHz, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input
10/100 Ethernet Mac With Dedicated Dma
supports IEEE 1588v2 hardware, MII/RMII
Cryptographic Acceleration
hardware acceleration for AES 128, 192, 256, Triple DES, HASH (MD5, SHA-1), and HMAC
Rtc
subsecond accuracy, hardware calendar

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Description
2.2.12
2.2.13
2.2.14
Note:
22/168
event (rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 140 GPIOs can be connected
to the 16 external interrupt lines.
Clocks and startup
On reset the 16 MHz internal RC oscillator is selected as the default CPU clock. The
16 MHz internal RC oscillator is factory-trimmed to offer 1% accuracy over the full
temperature range. The application can then select as system clock either the RC oscillator
or an external 4-26 MHz clock source. This clock can be monitored for failure. If a failure is
detected, the system automatically switches back to the internal RC oscillator and a
software interrupt is generated (if enabled). This clock source is input to a PLL thus allowing
to increase the frequency up to 168 MHz. Similarly, full interrupt management of the PLL
clock entry is available when necessary (for example if an indirectly used external oscillator
fails).
Several prescalers allow the configuration of the two AHB buses, the high-speed APB
(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the two AHB
buses is 168 MHz while the maximum frequency of the high-speed APB domains is 84 MHz.
The maximum allowed frequency of the low-speed APB domain is 42 MHz.
The devices embed a dedicated PLL (PLLI2S) which allows to achieve audio class
performance. In this case, the I
frequencies from 8 kHz to 192 kHz.
Boot modes
At startup, boot pins are used to select one out of three boot options:
The boot loader is located in system memory. It is used to reprogram the Flash memory by
using USART1 (PA9/PA10), USART3 (PC10/PC11 or PB10/PB11), CAN2 (PB5/PB13), USB
OTG FS in Device mode (PA11/PA12) through DFU (device firmware upgrade).
Power supply schemes
Refer to
V
temperature range and an inverted reset signal is applied to PDR_ON.
DD
/V
Boot from user Flash
Boot from system memory
Boot from embedded SRAM
V
enabled), provided externally through V
V
RCs and PLL. V
V
registers (through power switch) when V
DD
SSA
BAT
DDA
Figure 18: Power supply scheme
= 1.8 to 3.6 V: external power supply for I/Os and the internal regulator (when
, V
= 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup
minimum value of 1.7 V is obtained when the device operates in the 0 to 70 °C
DDA
= 1.8 to 3.6 V: external analog power supplies for ADC, DAC, Reset blocks,
DDA
and V
Doc ID 022063 Rev 2
2
SSA
S master clock can generate all standard sampling
must be connected to V
for more details.
DD
DD
pins.
is not present.
DD
STM32F415xx, STM32F417xx
and V
SS
, respectively.

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