STM32F417IE STMicroelectronics, STM32F417IE Datasheet - Page 25

• Manufacturer Part Number: STM32F417IE
• Description: High-performance and DSP with FPU, ARM Cortex-M4 MCU with 512 Kbytes Flash, 168 MHz CPU, Art Accelerator, Ethernet, HW crypto
• Manufacturer: STMicroelectronics

Specifications of STM32F417IE

• Core: ARM 32-bit Cortex™-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait state execution from Flash memory, frequency up to 168 MHz, memory protection unit, 210 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions
• 3×12-bit, 2.4 Msps A/d Converters: up to 24 channels and 7.2 MSPS in triple interleaved mode
• General-purpose Dma: 16-stream DMA controller with FIFOs and burst support
• Up To 17 Timers: up to twelve 16-bit and two 32-bit timers up to 168 MHz, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input
• 10/100 Ethernet Mac With Dedicated Dma: supports IEEE 1588v2 hardware, MII/RMII
• Cryptographic Acceleration: hardware acceleration for AES 128, 192, 256, Triple DES, HASH (MD5, SHA-1), and HMAC
• Rtc: subsecond accuracy, hardware calendar

STM32F415xx, STM32F417xx
Regulator OFF
This mode allows to power the device as soon as V
●
●
Regulator OFF/internal reset ON
This mode is available only on UFBGA package. It is activated by setting
BYPASS_REG and PDR_ON pins to V
The regulator OFF/internal reset ON mode allows to supply externally a 1.2 V voltage
source through V
The following conditions must be respected:
–
–
–
In regulator OFF/internal reset ON mode, PA0 cannot be used as a GPIO pin since it
allows to reset the part of the 1.2 V logic which is not reset by the NRST pin, when the
internal voltage regulator in off.
Regulator OFF/internal reset OFF
This mode is available only on UFBGA package. It is activated by setting
BYPASS_REG pin to V
allows to supply externally a 1.2 V voltage source through V
addition to V
The following conditions must be respected:
–
–
–
V
between power domains.
If the time for V
reach 1.8 V (V
operates in the 0 to 70 °C temperature range and PDR is disabled), then PA0
should be connected to the NRST pin (see
asserted low externally during POR until V
If V
must be asserted on PA0 pin.
V
between power domains.
PA0 should be kept low to cover both conditions: until V
1.08 V and until V
NRST should be controlled by an external reset controller to keep the device
under reset when V
DD
DD
CAP_1
should always be higher than V
should always be higher than V
DD
and V
.
CAP_1
DD
CAP_1
CAP_2
/V
DD
and V
DD
DDA
DD
Doc ID 022063 Rev 2
reaches 1.8 V (see
and V
and by applying an inverted reset signal to PDR_ON, and
go below 1.08 V and V
is below 1.8 V (see
minimum value of 1.7 V is obtained when the device
CAP_2
CAP_2
pins, in addition to V
to reach 1.08 V is faster than the time for V
DD
CAP_1
CAP_1
.
Figure
DD
and V
DD
and V
Figure
Figure
DD
reaches 1.8 V.
reaches 1.8 V (see
8).
is higher than 1.7 V, then a reset
CAP_2
CAP_2
9).
8). Otherwise, PA0 should be
DD
.
to avoid current injection
to avoid current injection
CAP_1
CAP_1
and V
and V
Figure
CAP_2
CAP_2
Description
9).
pins, in
reach
25/168
DD
to