STM32F407ZG STMicroelectronics, STM32F407ZG Datasheet - Page 108

no-image

STM32F407ZG

Manufacturer Part Number
STM32F407ZG
Description
High-performance and DSP with FPU, ARM Cortex-M4 MCU with 1 Mbyte Flash, 168 MHz CPU, Art Accelerator, Ethernet
Manufacturer
STMicroelectronics
Datasheet

Specifications of STM32F407ZG

Core
ARM 32-bit Cortex™-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait state execution from Flash memory, frequency up to 168 MHz, memory protection unit, 210 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions
3×12-bit, 2.4 Msps A/d Converters
up to 24 channels and 7.2 MSPS in triple interleaved mode
General-purpose Dma
16-stream DMA controller with FIFOs and burst support
Up To 17 Timers
up to twelve 16-bit and two 32-bit timers up to 168 MHz, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input
10/100 Ethernet Mac With Dedicated Dma
supports IEEE 1588v2 hardware, MII/RMII
Rtc
subsecond accuracy, hardware calendar

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
STM32F407ZGT6
Manufacturer:
STM
Quantity:
168
Part Number:
STM32F407ZGT6
Manufacturer:
STMicroelectronics
Quantity:
10 000
Part Number:
STM32F407ZGT6
Manufacturer:
ST
Quantity:
20 000
Part Number:
STM32F407ZGT6
Manufacturer:
ST
Quantity:
16 245
Part Number:
STM32F407ZGT6
0
Company:
Part Number:
STM32F407ZGT6
Quantity:
18 000
Part Number:
STM32F407ZGT6J
Manufacturer:
RENESAS
Quantity:
5 000
Part Number:
STM32F407ZGT7
Manufacturer:
ST
Quantity:
401
Part Number:
STM32F407ZGT7
Manufacturer:
ST
0
Part Number:
STM32F407ZGT7
0
Part Number:
STM32F407ZGTG
Manufacturer:
ST
0
Electrical characteristics
108/167
I
Unless otherwise specified, the parameters given in
are derived from tests performed under the ambient temperature, f
supply voltage conditions summarized in
Refer to
function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I
Table 52.
1. Remapped SPI1 characteristics to be determined.
2. TBD stands for “to be defined”.
3. Based on characterization, not tested in production.
4. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate
5. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put
2
DuCy(SCK)
t
t
t
dis(SO)
t
S - SPI interface characteristics
t
t
t
w(SCLH)
v(SO)
t
w(SCLL)
a(SO)
v(MO)
1/t
su(NSS)
t
Symbol
t
h(NSS)
t
t
t
su(MI)
t
h(MO)
the data.
the data in Hi-Z
su(SI)
h(MI)
h(SO)
t
t
h(SI)
r(SCL)
f
f(SCL)
c(SCK)
SCK
(3)(4)
(3)(1)
(3)(1)
(3)
(3)(5)
(3)
(3)
(3)
(3)
(3)
(3)
Section 5.3.16: I/O port characteristics
(3)
(3)
(3)
SPI characteristics
SPI clock frequency
SPI clock rise and fall
time
SPI slave input clock
duty cycle
NSS setup time
NSS hold time
SCK high and low time Master mode, f
Data input setup time
Data input hold time
Data output access
time
Data output disable
time
Data output valid time Slave mode (after enable edge)
Data output valid time Master mode (after enable edge)
Data output hold time
Parameter
Doc ID 022152 Rev 2
(1)(2)
Master mode
Slave mode
Capacitive load: C = 30 pF
Slave mode
Slave mode
Slave mode
Master mode
Slave mode
Master mode
Slave mode
Slave mode, f
Slave mode
Slave mode (after enable edge)
Master mode (after enable edge)
Table
Conditions
11.
for more details on the input/output alternate
PCLK
PCLK
= 20 MHz
Table 52
= TBD MHz
STM32F405xx, STM32F407xx
for SPI or in
PCLKx
4t
2t
TBD
Min
PCLK
PCLK
30
15
5
5
5
4
2
2
-
-
-
-
-
0
frequency and V
Table 53
3 t
TBD
Max
37.5
37.5
70
10
25
2
PCLK
-
-
-
8
-
-
-
-
5
-
S).
for I
MHz
Unit
ns
ns
%
2
S
DD

Related parts for STM32F407ZG