STM32F407ZG STMicroelectronics, STM32F407ZG Datasheet - Page 125

• Manufacturer Part Number: STM32F407ZG
• Description: High-performance and DSP with FPU, ARM Cortex-M4 MCU with 1 Mbyte Flash, 168 MHz CPU, Art Accelerator, Ethernet
• Manufacturer: STMicroelectronics

Specifications of STM32F407ZG

• Core: ARM 32-bit Cortex™-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait state execution from Flash memory, frequency up to 168 MHz, memory protection unit, 210 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions
• 3×12-bit, 2.4 Msps A/d Converters: up to 24 channels and 7.2 MSPS in triple interleaved mode
• General-purpose Dma: 16-stream DMA controller with FIFOs and burst support
• Up To 17 Timers: up to twelve 16-bit and two 32-bit timers up to 168 MHz, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input
• 10/100 Ethernet Mac With Dedicated Dma: supports IEEE 1588v2 hardware, MII/RMII
• Rtc: subsecond accuracy, hardware calendar

STM32F405xx, STM32F407xx
Table 70.
1. If an inverted reset signal is applied to PDR_ON, this value can be lowered to 1.7 V when the device operates in a reduced
2. Guaranteed by design, not tested in production.
3. Guaranteed by characterization, not tested in production.
INL
Offset
Gain
error
t
THD
Update
rate
t
PSRR+
SETTLING
WAKEUP
Symbol
temperature range (0 to 70 °C).
(3)
(2)
(3)
(3)
(3)
(2)
(3)
(3)
Integral non linearity
(difference between
measured value at Code i
and the value at Code i on a
line drawn between Code 0
and last Code 1023)
Offset error
(difference between
measured value at Code
(0x800) and the ideal value =
V
Gain error
Settling time (full scale: for a
10-bit input code transition
between the lowest and the
highest input codes when
DAC_OUT reaches final
value ±4LSB
Total Harmonic Distortion
Buffer ON
Max frequency for a correct
DAC_OUT change when
small variation in the input
code (from code i to i+1LSB)
Wakeup time from off state
(Setting the ENx bit in the
DAC Control register)
Power supply rejection ratio
(to V
measurement)
DAC characteristics (continued)
REF+
DDA
/2)
) (static DC
Parameter
Min
-
-
-
-
-
-
-
-
-
-
-
Doc ID 022152 Rev 2
Typ
–67
6.5
3
-
-
-
-
-
-
-
-
Max
±0.5
±10
±12
–40
±1
±4
±3
10
6
1
-
MS/s
Unit
LSB
LSB
LSB
LSB
mV
dB
dB
µs
µs
%
Given for the DAC in 10-bit
configuration.
Given for the DAC in 12-bit
configuration.
Given for the DAC in 12-bit
configuration
Given for the DAC in 10-bit at
V
Given for the DAC in 12-bit at
V
Given for the DAC in 12-bit
configuration
C
R
C
R
C
R
C
input code between lowest and
highest possible ones.
No R
REF+
REF+
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
Electrical characteristics
= 3.6 V
= 3.6 V
≤ 50 pF,
≥ 5 kΩ
≤ 50 pF,
≥ 5 kΩ
≤ 50 pF,
≥ 5 kΩ
≤ 50 pF, R
, C
Comments
LOAD
LOAD
= 50 pF
≥ 5 kΩ
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