STM8AF52AA STMicroelectronics, STM8AF52AA Datasheet - Page 14

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STM8AF52AA

Manufacturer Part Number
STM8AF52AA
Description
STM8AF52 CAN Line
Manufacturer
STMicroelectronics
Datasheet

Specifications of STM8AF52AA

Max Fcpu
24 MHz
Program Memory
32 to 128 Kbytes Flash program; data retention 20 years at 55 °C
Data Memory
up to 2 Kbytes true data EEPROM; endurance 300 kcycles
Ram
2 Kbytes to 6 Kbytes
Advanced Control Timer
16-bit, 4 CAPCOM channels, 3 complementary outputs, dead-time insertion and flexible synchronization

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Product overview
5
5.1
5.1.1
5.1.2
5.1.3
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Product overview
This section is intended to describe the family features that are actually implemented in the
products covered by this datasheet.
For more detailed information on each feature please refer to the STM8S and STM8A
microcontroller families reference manual (RM0016).
STM8A central processing unit (CPU)
The 8-bit STM8A core is a modern CISC core and has been designed for code efficiency
and performance. It contains 21 internal registers (six directly addressable in each execution
context), 20 addressing modes including indexed indirect and relative addressing and 80
instructions.
Architecture and registers
Addressing
Instruction set
Harvard architecture
3-stage pipeline
32-bit wide program memory bus with single cycle fetching for most instructions
X and Y 16-bit index registers, enabling indexed addressing modes with or without
offset and read-modify-write type data manipulations
8-bit accumulator
24-bit program counter with 16-Mbyte linear memory space
16-bit stack pointer with access to a 64 Kbyte stack
8-bit condition code register with seven condition flags for the result of the last
instruction.
20 addressing modes
Indexed indirect addressing mode for look-up tables located anywhere in the address
space
Stack pointer relative addressing mode for efficient implementation of local variables
and parameter passing
80 instructions with 2-byte average instruction size
Standard data movement and logic/arithmetic functions
8-bit by 8-bit multiplication
16-bit by 8-bit and 16-bit by 16-bit division
Bit manipulation
Data transfer between stack and accumulator (push/pop) with direct stack access
Data transfer using the X and Y registers or direct memory-to-memory transfers
Doc ID 14395 Rev 8
STM8AF52/62xx, STM8AF51/61xx

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