STM8S207RB STMicroelectronics, STM8S207RB Datasheet - Page 77

• Manufacturer Part Number: STM8S207RB
• Description: Performance line, 24 MHz STM8S 8-bit MCU, up to 128 Kbytes Flash, integrated EEPROM
• Manufacturer: STMicroelectronics

Specifications of STM8S207RB

• Max Fcpu: up to 24 MHz, 0 wait states @ fCPU≤ 16 MHz
• Program: up to 128 Kbytes Flash; data retention 20 years at 55 °C after 10 kcycles
• Data: up to 2 Kbytes true data EEPROM; endurance 300 kcycles
• Ram: up to 6 Kbytes
• Advanced Control Timer: 16-bit, 4 CAPCOM channels, 3 complementary outputs, dead-time insertion and flexible synchronization

STM8S207xx, STM8S208xx
10.3.8
Table 42.
1. Values based on design simulation and/or characterization results, and not tested in production.
2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.
3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z.
t
t
t
t
dis(SO)
t
w(SCKH)
t
w(SCKL)
a(SO)
1/t
su(NSS)
t
Symbol
t
t
t
h(NSS)
t
t
t
su(MI)
t
v(SO)
h(MO)
su(SI)
v(MO)
h(SO)
t
h(MI)
t
h(SI)
r(SCK)
f(SCK)
f
c(SCK)
SCK
(1)(2)
(1)
(1)(3)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
SPI serial peripheral interface
Unless otherwise specified, the parameters given in
performed under ambient temperature, f
conditions. t
Refer to I/O port characteristics for more details on the input/output alternate function
characteristics (NSS, SCK, MOSI, MISO).
SPI characteristics
SPI clock frequency
SPI clock rise and fall time
NSS setup time
NSS hold time
SCK high and low time
Data input setup time
Data input hold time
Data output access time
Data output disable time
Data output valid time
Data output valid time
Data output hold time
Parameter
MASTER
= 1/f
MASTER
Slave mode
Master mode
Slave mode
Slave mode
Slave mode (after enable edge)
Master mode (after enable edge)
Master mode
Slave mode
Capacitive load: C = 30 pF
Slave mode
Master mode
Slave mode
Master mode
Slave mode
Slave mode (after enable edge)
Master mode (after enable edge)
Doc ID 14733 Rev 12
.
Conditions
MASTER
frequency and V
Table 42
4 x t
t
SCK
are derived from tests
Min
MASTER
70
10
25
31
12
/2 - 15
0
5
5
7
DD
0
Electrical characteristics
supply voltage
t
3 x t
SCK
Max
10
25
/2 + 15
MASTER
75
30
6
77/103
Unit
MHz
ns