STM8S003F3 STMicroelectronics, STM8S003F3 Datasheet
STM8S003F3
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STM8S003F3 Summary of contents
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... Low power modes (wait, active-halt, halt) - Switch-off peripheral clocks individually • Permanently active, low consumption power-on and power-down reset January 2012 STM8S003K3 STM8S003F3 Interrupt management • Nested interrupt controller with 32 interrupts • external interrupts on 6 vectors Timers • Advanced control timer: 16-bit, 4 CAPCOM ...
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... UART1 ...............................................................................................16 4.14.2 SPI .....................................................................................................17 4.14.3 I²C ......................................................................................................17 5 Pinout and pin description ...................................................................................18 5.1 STM8S003K3 LQFP32 pinout and pin description ......................................................18 5.2 STM8S003F3 TSSOP20/UFQFPN20 pinout and pin description ...............................21 5.2.1 STM8S003F3 TSSOP20 pinout and pin description ............................21 5.2.2 STM8S003F3 UFQFPN20 pinout ........................................................22 5.2.3 STM8S003F3 TSSOP20/UFQFPN20 pin description ..........................22 5.3 Alternate function remapping .......................................................................................24 6 Memory and register map .....................................................................................25 6 ...
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... STM8S003K3 STM8S003F3 9 Electrical characteristics ......................................................................................46 9.1 Parameter conditions ...................................................................................................46 9.1.1 Minimum and maximum values ...........................................................46 9.1.2 Typical values .......................................................................................46 9.1.3 Typical curves ......................................................................................46 9.1.4 Loading capacitor .................................................................................46 9.1.5 Pin input voltage ...................................................................................46 9.2 Absolute maximum ratings ..........................................................................................47 9.3 Operating conditions ....................................................................................................49 9.3.1 VCAP external capacitor ......................................................................50 9.3.2 Supply current characteristics ..............................................................51 9.3.3 External clock sources and timing characteristics ...............................60 9.3.4 Internal clock sources and timing characteristics .................................62 9 ...
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... Table 10. Interrupt mapping ...................................................................................................................39 Table 11. Option bytes ...........................................................................................................................98 Table 12. Option byte description ...........................................................................................................41 Table 13. STM8S003K3 alternate function remapping bits for 32-pin devices ......................................43 Table 14. STM8S003F3 alternate function remapping bits for 20-pin devices ......................................44 Table 15. Voltage characteristics ...........................................................................................................47 Table 16. Current characteristics ...........................................................................................................47 Table 17. Thermal characteristics ..........................................................................................................48 Table 18. General operating conditions .................................................................................................49 Table 19 ...
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... STM8S003K3 STM8S003F3 Table 48. EMI data .................................................................................................................................86 Table 49. ESD absolute maximum ratings .............................................................................................87 Table 50. Electrical sensitivities .............................................................................................................88 Table 51. 32-pin low profile quad flat package mechanical data ............................................................89 Table 52. 20-pin, 4.40 mm body, 0.65 mm pitch mechanical data .........................................................91 Table 53. 20-lead ultra thin fine pitch quad flat no-lead package (3x3) mechanical data ......................92 Table 54 ...
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... List of figures List of figures Figure 1. Block diagram ...........................................................................................................................9 Figure 2. Flash memory organization ....................................................................................................12 Figure 3. STM8S003K3 LQFP32 pinout ................................................................................................18 Figure 4. STM8S003F3 TSSOP20 pinout ..............................................................................................21 Figure 5. STM8S003F3 UFQFPN20-pin pinout .....................................................................................22 Figure 6. Memory map ...........................................................................................................................25 Figure 7. Pin loading conditions .............................................................................................................46 Figure 8. Pin input voltage .....................................................................................................................47 Figure 9. f versus V CPUmax DD Figure 10. External capacitor C Figure 11 ...
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... STM8S003K3 STM8S003F3 1 Introduction This datasheet contains the description of the device features, pinout, electrical characteristics, mechanical data and ordering information. • For complete information on the STM8S microcontroller memory, registers and peripherals, please refer to the STM8S microcontroller family reference manual (RM0016). • For information on programming, erasing and protection of the internal Flash memory please refer to the STM8S Flash programming manual (PM0051). • ...
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... Without read-while-write capability. 8/99 Table 1: STM8S003xx value line features STM8S003K3 (1) 128 Multipurpose timer (TIM1), SPI, I window WDG,independent WDG, ADC, PWM timer (TIM2), 8-bit timer (TIM4) DocID018576 Rev 2 STM8S003K3 STM8S003F3 STM8S003F3 (1) 128 2 C, UART ...
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... STM8S003K3 STM8S003F3 3 Block diagram Reset block Reset POR Single wire Debug/SWIM debug interf. 400 Kbit/s 8 Mbit/s LIN master SPI emul channels 1/2/4 kHz beep Figure 1: Block diagram Clock controller Reset Detector BOR Clock to peripherals and core STM8 core SPI UART1 ...
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... Data transfer between stack and accumulator (push/pop) with direct stack access • Data transfer using the X and Y registers or direct memory-to-memory transfers 4.2 Single wire interface module (SWIM) and debug module (DM) The single wire interface module and debug module permits non-intrusive, real-time in-circuit debugging and fast memory programming. 10/99 DocID018576 Rev 2 STM8S003K3 STM8S003F3 ...
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... STM8S003K3 STM8S003F3 SWIM Single wire interface module for direct access to the debug module and memory programming. The interface can be activated in all device operation modes. The maximum data transmission speed is 145 bytes/ms. Debug module The non-intrusive debugging module features a performance close to a full-featured emulator. ...
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... UBC area Remains write protected during IAP Low density Flash program memory (8 Kbytes) Program memory area Write access possible for IAP MASTER DocID018576 Rev 2 STM8S003K3 STM8S003F3 Programmable area from 64 bytes(1 page Kbytes (in 1 page steps) ) coming from different oscillators ...
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... STM8S003K3 STM8S003F3 • Startup clock: After reset, the microcontroller restarts by default with an internal 2 MHz clock (HSI/8). The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts. • Clock security system (CSS): This feature can be enabled by software HSE clock failure occurs, the internal RC (16 MHz/8) is automatically selected by the CSS and an interrupt can optionally be generated ...
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... PWM generation (edge and center aligned mode) and single pulse mode output • Synchronization module to control the timer with external signals • Break input to force the timer outputs into a defined state • Three complementary outputs with adjustable dead time 14/99 DocID018576 Rev 2 STM8S003K3 STM8S003F3 ...
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... STM8S003K3 STM8S003F3 • Encoder mode • Interrupt sources input capture/output compare overflow/update break 4.11 TIM2 - 16-bit general purpose timer • 16-bit autoreload (AR) up-counter • 15-bit prescaler adjustable to fixed power of 2 ratios 1…32768 • 3 individually configurable capture/compare channels • PWM mode • ...
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... Separate enable bits for transmitter and receiver • Two receiver wakeup modes: - Address bit (MSB) - Idle line (interrupt) • Transmission error detection with interrupt generation • Parity control Synchronous communication • Full duplex synchronous transfers 16/99 DocID018576 Rev 2 STM8S003K3 STM8S003F3 /16) and capable of CPU ...
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... STM8S003K3 STM8S003F3 • SPI master operation • 8-bit data communication • Maximum speed: 1 Mbit MHz (f LIN master mode • Emission: Generates 13-bit synch break frame • Reception: Detects 11-bit break frame 4.14.2 SPI • Maximum speed: 8 Mbit/s (f • Full duplex synchronous transfers • ...
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... NRST 2 OSCIN/PA1 3 OSCOUT/PA2 VCAP [SPI_NSS] TIM2_CH3/(HS)PA3 8 PF4 DocID018576 Rev 2 STM8S003K3 STM8S003F3 24 PC7 (HS)/SPI_MISO 23 PC6 (HS)/SPI_MOSI 22 PC5 (HS)/SPI_SCK 21 PC4 (HS)/TIM1_CH4/CLK_CCO 20 PC3 (HS)/TIM1_CH3 19 PC2 (HS)/TIM1_CH2 18 PC1 (HS)/TIM1_CH1/ UART1_CK 17 PE5 (HS) ...
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... STM8S003K3 STM8S003F3 1. (HS) high sink capability. 2. (T) True open drain (P-buffer and protection diode alternate function remapping option (if the same alternate function is shown twice, it indicates an exclusive choice not a duplication of the function). Input Pin Pin Type no. name floating 1 NRST I/O (2) 2 PA1/ OSCI ...
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... DocID018576 Rev 2 STM8S003K3 STM8S003F3 Main Default function alternate (after reset) function PP X Port B1 Analog input 1/ Timer 1 - inverted channel 2 X Port B0 Analog input 0/ Timer 1 - inverted channel 1 X Port E5 SPI master/slave select ...
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... In the open-drain output column, "T" defines a true open-drain I/O (P-buffer, weak pull-up, and protection diode are not implemented). (4) The PD1 pin is in input pull-up during the reset phase and after internal reset release. 5.2 STM8S003F3 TSSOP20/UFQFPN20 pinout and pin description 5.2.1 STM8S003F3 TSSOP20 pinout and pin description 1. HS high sink capability. Output Ext. High wpu Speed ...
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... PC7(HS)/SPI_MISO[TIM1_CH2] OSCOUT/PA2 3 13 PC6(HS)/SPI_MOSI [TIM1_CH1 PC5 (HS)/SPI_SCK [TIM2_CH1] 12 VCAP 5 PC4(HS)/TIM1_CH4/CLK_CCO/AIN2/[TIM1_CH2N Table 6: STM8S003F3 pin description Input Output High Type Ext. floating wpu sink Speed interr. (1) I DocID018576 Rev 2 STM8S003K3 STM8S003F3 not implemented). ...
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... STM8S003K3 STM8S003F3 Pin no. Pin name TSSOP20 UFQFPN20 2 19 PD5/ AIN5/ UART1 _TX 3 20 PD6/ AIN6/ UART1 _RX 4 1 NRST 5 2 PA1/ OSCIN ( PA2/ OSCOUT VCAP PA3/ TIM2_ CH3 [SPI_ NSS PB5 SDA [TIM1_ ...
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... DocID018576 Rev 2 STM8S003K3 STM8S003F3 Main Alternate Default function function after alternate (after remap [option OD PP function reset) bit Port SPI master Timer out/slave in channel 1 [AFR0 Port SPI master ...
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... STM8S003K3 STM8S003F3 6 Memory and register map 6.1 Memory map Figure 6: Memory map 0x00 0000 RAM (1 Kbyte) 513 bytes stack 0x00 03FF 0x00 0800 Reserved 0x00 4000 Data EEPROM 0x00 407F Reserved 0x00 47FF 0x00 4800 Option bytes 0x00 480A 0x00 480B Reserved ...
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... Port D control register 1 PD_CR2 Port D control register 2 PE_ODR Port E data output latch register PE_IDR Port E input pin value register PE_DDR Port E data direction register PE_CR1 Port E control register 1 DocID018576 Rev 2 STM8S003K3 STM8S003F3 Reset status 0x00 (1) 0xXX 0x00 0x00 0x00 0x00 (1) 0xXX ...
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... STM8S003K3 STM8S003F3 Address Block 0x00 5018 Port E 0x00 5019 0x00 501A Port F 0x00 501B 0x00 501C 0x00 501D (1) Depends on the external circuitry. 6.2.2 General hardware register map Address Block 0x00 501E to Reserved area (60 bytes) 0x00 5059 0x00 505A Flash 0x00 505B 0x00 505C ...
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... Clock switch control register CLK_CKDIVR Clock divider register CLK_PCKENR1 Peripheral clock gating register 1 CLK_CSSR Clock security system register CLK_CCOR Configurable clock control register CLK_PCKENR2 Peripheral clock gating register 2 DocID018576 Rev 2 STM8S003K3 STM8S003F3 Reset status 0x00 0x00 0x00 (1) 0xXX 0x01 0x00 0xE1 0xE1 ...
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... STM8S003K3 STM8S003F3 Address Block 0x00 50CC 0x00 50CD 0x00 50CE to ReservLK ed area (3 bytes) 0x00 50D0 0x00 50D1 WWDG 0x00 50D2 0x00 50D3 to 00 Reserved area (13 bytes) 50DF 0x00 50E0 IWDG 0x00 50E1 0x00 50E2 0x00 50E3 to Reserved area (13 bytes) 0x00 50EF ...
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... I2C_SR2 I C status register 2 2 I2C_SR3 I C status register 3 2 I2C_ITR I C interrupt control register 2 I2C_CCRL I C Clock control register low DocID018576 Rev 2 STM8S003K3 STM8S003F3 Reset status 0x00 0x02 0x00 0x07 0xFF 0xFF 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 ...
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... STM8S003K3 STM8S003F3 Address Block 0x00 521C 0x00 521D 0x00 521E 0x00 521F to Reserved area (17 bytes) 0x00 522F 0x00 5230 UART1 0x00 5231 0x00 5232 0x00 5233 0x00 5234 0x00 5235 0x00 5236 0x00 5237 0x00 5238 0x00 5239 0x00 523A 0x00 523B to ...
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... TIM1 counter low TIM1_PSCRH TIM1 prescaler register high TIM1_PSCRL TIM1 prescaler register low TIM1_ARRH TIM1 auto-reload register high TIM1_ARRL TIM1 auto-reload register low TIM1_RCR TIM1 repetition counter register DocID018576 Rev 2 STM8S003K3 STM8S003F3 Reset status 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 ...
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... STM8S003K3 STM8S003F3 Address Block 0x00 5265 0x00 5266 0x00 5267 0x00 5268 0x00 5269 0x00 526A 0x00 526B 0x00 526C 0x00 526D 0x00 526E 0x00 526F 0x00 5270 to Reserved area (147 bytes) 0x00 52FF 0x00 5300 TIM2 0x00 5301 0x00 5302 ...
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... TIM2_CCR2H TIM2 capture/compare reg. 2 high TIM2_CCR2L TIM2 capture/compare register 2 low TIM2_CCR3H TIM2 capture/compare register 3 high TIM2_CCR3L TIM2 capture/compare register 3 low TIM4_CR1 TIM4 control register 1 Reserved DocID018576 Rev 2 STM8S003K3 STM8S003F3 Reset status 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xFF 0xFF ...
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... STM8S003K3 STM8S003F3 Address Block 0x00 5342 0x00 5343 0x00 5344 0x00 5345 0x00 5346 0x00 5347 0x00 5348 0x00 5349 to Reserved area (153 bytes) 0x00 53DF 0x00 53E0 to ADC1 0x00 53F3 0x00 53F4 to Reserved area (12 bytes) 0x00 53FF 0x00 5400 ADC1 ...
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... Register name A Accumulator PCE Program counter extended PCH Program counter high PCL Program counter low XH X index register high XL X index register low DocID018576 Rev 2 STM8S003K3 STM8S003F3 Reset status 0x03 0xFF 0x00 0x00 0x00 0x00 0x00 0x00 Reset status 0x00 0x00 ...
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... STM8S003K3 STM8S003F3 Address Block 0x00 7F06 0x00 7F07 0x00 7F08 0x00 7F09 0x00 7F0A 0x00 7F0B to 0x00 7F5F 0x00 7F60 CPU 0x00 7F70 0x00 7F71 0x00 7F72 0x00 7F73 ITC 0x00 7F74 0x00 7F75 0x00 7F76 0x00 7F77 0x00 7F78 to 0x00 7F79 ...
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... Accessible by debug module only 38/99 Register label Register name DM_CSR1 DM debug module control/status register 1 DM_CSR2 DM debug module control/status register 2 DM_ENFCTR DM enable function register Reserved area (5 bytes) DocID018576 Rev 2 STM8S003K3 STM8S003F3 Reset status 0x10 0x00 0xFF ...
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... STM8S003K3 STM8S003F3 7 Interrupt vector mapping IRQ Source Description no. block RESET Reset TRAP Software interrupt 0 TLI External top level interrupt 1 AWU Auto wake up from halt 2 CLK Clock controller 3 EXTI0 Port A external interrupts 4 EXTI1 Port B external interrupts 5 EXTI2 Port C external interrupts 6 EXTI3 Port D external interrupts ...
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... Interrupt vector mapping IRQ Source Description no. block 23 TIM4 TIM4 update/ overflow 24 Flash EOP/WR_PG_DIS (1) Except PA1 40/99 Wakeup from halt mode - - Reserved DocID018576 Rev 2 STM8S003K3 STM8S003F3 Wakeup from Vector address active-halt mode - 0x00 8064 - 0x00 8068 0x00 806C to 0x00 807C ...
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... STM8S003K3 STM8S003F3 8 Option bytes Option bytes contain configurations for device hardware features as well as the memory protection of the device. They are stored in a dedicated block of the memory. Except for the ROP (read-out protection) byte, each option byte has to be stored twice regular form (OPTx) and a complemented one (NOPTx) for redundancy ...
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... LSI clock is available as CPU clock source IWDG_HW: Independent watchdog 0: IWDG Independent watchdog activated by software 1: IWDG Independent watchdog activated by hardware WWDG_HW: Window watchdog activation 0: WWDG window watchdog activated by software 1: WWDG window watchdog activated by hardware WWDG_HALT: Window watchdog reset on halt DocID018576 Rev 2 STM8S003K3 STM8S003F3 ...
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... STM8S003K3 STM8S003F3 Option byte no. OPT4 OPT5 8.1 Alternate function remapping bits Table 13: STM8S003K3 alternate function remapping bits for 32-pin devices Option byte no. OPT2 Description 0: No reset generated on halt if WWDG active 1: Reset generated on halt if WWDG active EXTCLK: External clock selection 0: External crystal connected to OSCIN/OSCOUT ...
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... Option bytes Option byte no. (1) Do not use more than one remapping option in the same port forbidden to enable both AFR1 and AFR0. (2) Refer to pinout description. Table 14: STM8S003F3 alternate function remapping bits for 20-pin devices Option byte no. OPT2 44/99 (1) Description 1: Port D0 alternate function = CLK_CCO. ...
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... STM8S003K3 STM8S003F3 Option byte no. (1) Refer to pinout description. (2) Do not use more than one remapping option in the same port forbidden to enable both AFR1 and AFR0. Description Reserved AFR1 Alternate function remapping option 1 0: AFR1 remapping option inactive: Default alternate (1) functions . 1: Port A3 alternate function = SPI_NSS ...
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... The loading conditions used for pin parameter measurement are shown in the following figure. 9.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in the following figure. 46/ °C and ° Figure 7: Pin loading conditions STM8 pin 50 pF DocID018576 Rev 2 STM8S003K3 STM8S003F3 . = T (given by A Amax = 5 V. They are given DD ...
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... STM8S003K3 STM8S003F3 9.2 Absolute maximum ratings Stresses above those listed as ‘absolute maximum ratings’ may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability ...
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... J 48/99 ground lines (sink) SS (5) ) pins must always be connected to the external supply. SS while a negative injection is induced maximum current injection on four I/O port pins of the device. Table 17: Thermal characteristics DocID018576 Rev 2 STM8S003K3 STM8S003F3 (1) Max ( ± 4 ± 4 ± 4 (5) ± 20 maximum is respected ...
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... STM8S003K3 STM8S003F3 9.3 Operating conditions Symbol Parameter f Internal CPU clock frequency CPU V Standard operating voltage DD (1) VCAP C : capacitance of EXT external capacitor ESR of external capacitor ESL of external capacitor ( Power dissipation at T for suffix 6 T Ambient temperature for 6 suffix A version T Junction temperature range for ...
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... Conditions (1) V rising DD delay. The application must ensure that V TEMP min) when the t delay has elapsed. DD TEMP Figure 10: External capacitor C C ESR Rleak DocID018576 Rev 2 STM8S003K3 STM8S003F3 versus V DD 5.0 5.5 Supply voltage Min Typ Max 2 ∞ 2 ∞ 1.7 2.6 2.7 2.85 2.5 2.65 2 still above the ...
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... STM8S003K3 STM8S003F3 9.3.2 Supply current characteristics The current consumption is measured as described in 9.3.2.1 Total current consumption in run mode The MCU is placed under the following conditions: • All I/O pins in input mode with a static value at V • All peripherals are disabled (clock stopped by peripheral clock gating registers) except if explicitly mentioned ...
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... LSI RC osc. (128 kHz) HSE crystal osc. (16 MHz MASTER HSE user ext. clock (16 MHz) HSI RC osc. (16 MHz MASTER HSI RC osc. (16 MHz/ MASTER HSI RC osc. (16 MHz MASTER HSI RC osc. (16 MHz/ MASTER LSI RC osc. (128 kHz) DocID018576 Rev 2 STM8S003K3 STM8S003F3 = 3 Typ Unit (1) Max 1.8 2 2.3 1.5 2 0.81 0.7 0.87 0.46 0.58 0.41 0. 3.9 4.7 3.7 4 ...
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... STM8S003K3 STM8S003F3 9.3.2.2 Total current consumption in wait mode Table 22: Total current consumption in wait mode at V Symbol Parameter Conditions CPU 16 MHz CPU MASTER Supply 125 kHz I current in DD(WFI) wait mode CPU MASTER 15.625 kHz CPU 128 kHz (1) Data based on characterization results, not tested in production. ...
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... Operating mode Operating mode Power-down mode Power-down mode Operating mode Power-down mode (3) Flash mode Clock source (2) HSE crystal osc. On Operating mode (16 MHz) DocID018576 Rev 2 STM8S003K3 STM8S003F3 = Max at 85 Typ °C Clock source (1) HSE crystal osc. 1030 (16 MHz) LSI RC osc. 200 260 (128 kHz) HSE crystal osc ...
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... STM8S003K3 STM8S003F3 Conditions Main voltage Symbol Parameter regulator (MVR) I DD(AH) Supply current in active halt mode I DD(AH) I DD(AH) Supply current in I active halt mode DD(AH) I DD(AH) (1) Data based on characterization results, not tested in production (2) Configured by the REGAH bit in the CLK_ICKR register. (3) Configured by the AHALT bit in the FLASH_CR1 register. ...
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... MVR voltage Flash in operating regulator (5) mode (4) off MVR voltage Flash in regulator power-down (4) (5) off mode (5) Flash in operating mode (5) Flash in power-down mode CPU. DocID018576 Rev 2 STM8S003K3 STM8S003F3 Max at 85 Typ Unit °C (1) 4.5 17 (1) Typ Unit Max See (2) note 0.56 HSI (6) (6) (after 1 2 ...
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... STM8S003K3 STM8S003F3 (3) Measured from interrupt event to interrupt vector fetch. (4) Configured by the REGAH bit in the CLK_ICKR register. (5) Configured by the AHALT bit in the FLASH_CR1 register. (6) Plus 1 LSI clock depending on synchronization. 9.3.2.6 Total current consumption and timing in forced reset state Table 29: Total current consumption and timing in forced reset state ...
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... DD measurement between the on-chip peripheral when kept under reset DD measurement between reset configuration and continuous A/D DD vs. V HSE user external clock, f DD(RUN) DD vs. f HSE user external clock, V DD(RUN) CPU DocID018576 Rev 2 STM8S003K3 STM8S003F3 = 16 MHz CPU = ...
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... STM8S003K3 STM8S003F3 Figure 13: Typ I Figure 14: Typ I vs. V HSI RC osc, f DD(RUN) DD vs. V HSE user external clock, f DD(WFI) DD DocID018576 Rev 2 Electrical characteristics = 16 MHz CPU = 16 MHz CPU 59/99 ...
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... OSCIN input leakage current LEAK_HSE 60/99 vs. f HSE user external clock, V DD(WFI) CPU vs. V HSI RC osc, f DD(WFI) DD and Conditions Min 0 0 < V < DocID018576 Rev 2 STM8S003K3 STM8S003F3 = MHz CPU Max 0 0 Unit μA ...
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... STM8S003K3 STM8S003F3 (1) Data based on characterization results, not tested in production. V HSEH V HSEL HSE crystal/ceramic resonator oscillator The HSE clock can be supplied with MHz crystal/ceramic resonator oscillator. All the information given in this paragraph is based on characterization results with specified typical external components. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time ...
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... Frequency HSI 62/99 Figure 18: HSE oscillator circuit diagram OSCIN Resonator OSCOUT C L2 equation × R (2Co + Table 33: HSI oscillator characteristics Conditions DocID018576 Rev 2 STM8S003K3 STM8S003F3 f HSE to core Consumption control STM8 and Min Typ Max 16 Unit MHz ...
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... STM8S003K3 STM8S003F3 Symbol Parameter ACC Accuracy of HSI HSI oscillator Accuracy of HSI oscillator (factory calibrated) t HSI oscillator su(HSI) wakeup time including calibration I HSI oscillator DD(HSI) power consumption (1) Refer to application note. (2) Data based on characterization results, not tested in production. (3) Guaranteed by design, not tested in production. ...
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... Guaranteed by design, not tested in production. (2) Refer to the Operating conditions section for the value of V 64/99 and T DD Table 34: LSI oscillator characteristics Typ Table 35: RAM and hardware registers Conditions Halt mode (or reset) DocID018576 Rev 2 STM8S003K3 STM8S003F3 . A Max Unit 128 kHz 7 μs 5 μ temperatures ...
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... STM8S003K3 STM8S003F3 Flash program memory and data EEPROM Symbol Parameter V Operating voltage (all DD modes, execution/ write/erase) t Standard programming time prog (including erase) for byte/word/block (1 byte/ 4 bytes/64 bytes) Fast programming time for 1 block (64 bytes) t Erase time for 1 block erase (64 bytes) N Erase/write cycles ...
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... Fast I/Os Load = 50 pF Standard and high sink I/Os Load = ≤ V ≤ ≤ V ≤ Injection current ±4 mA DocID018576 Rev 2 STM8S003K3 STM8S003F3 unless otherwise specified. All unused A Min Typ Max 0 0.3 DD 700 (2) 20 ...
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... STM8S003K3 STM8S003F3 Figure 21: Typical V Figure 22: Typical pull-up resistance vs V and temperatures DocID018576 Rev 2 Electrical characteristics @ 4 temperatures 67/99 ...
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... Table 39: Output driving current (true open drain ports) Symbol Parameter Output low level with 2 pins sunk V OL Output low level with 2 pins sunk V OL 68/99 Table 38: Output driving current (standard ports) DocID018576 Rev 2 STM8S003K3 STM8S003F3 @ 4 temperatures DD Conditions Min Max mA ...
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... STM8S003K3 STM8S003F3 Symbol Parameter Output low level with 2 pins sunk V OL (1) Data based on characterization results, not tested in production Symbol Parameter Output low level with 8 pins sunk V OL Output low level with 4 pins sunk V OL Output low level with 4 pins sunk Output high level with 8 pins sourced ...
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... Electrical characteristics 70/99 Figure 24: Typ (standard ports Figure 25: Typ 3.3 V (standard ports DocID018576 Rev 2 STM8S003K3 STM8S003F3 ...
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... STM8S003K3 STM8S003F3 Figure 26: Typ. V Figure 27: Typ (true open drain ports 3.3 V (true open drain ports DocID018576 Rev 2 Electrical characteristics 71/99 ...
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... Electrical characteristics 72/99 Figure 28: Typ (high sink ports Figure 29: Typ 3.3 V (high sink ports DocID018576 Rev 2 STM8S003K3 STM8S003F3 ...
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... STM8S003K3 STM8S003F3 Figure 31: Typ. V Figure 30: Typ DocID018576 Rev 2 Electrical characteristics = 5 V (standard ports 3.3 V (standard ports) DD 73/99 ...
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... Subject to general operating conditions for V Symbol Parameter V IL(NRST) NRST input low 74/99 Figure 32: Typ Table 41: NRST pin characteristics Conditions Min -0.3 V DocID018576 Rev 2 STM8S003K3 STM8S003F3 = 5 V (high sink ports 3.3 V (high sink ports) DD and T unless otherwise specified. A Typ Max 0 Unit V ...
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... STM8S003K3 STM8S003F3 Symbol Parameter (1) level voltage V IH(NRST) NRST input high level voltage V OL(NRST) NRST output low level voltage R PU(NRST) NRST pull-up (2) resistor t I FP(NRST) NRST input filtered (3) pulse t IN FP(NRST) NRST input not filtered pulse t OP(NRST) NRST output (3) pulse (1) Data based on characterization results, not tested in production. ...
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... Electrical characteristics Figure 34: Typical NRST V Figure 35: Typical NRST pull-up resistance vs V 76/99 and temperatures DocID018576 Rev 2 STM8S003K3 STM8S003F3 @ 4 temperatures DD ...
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... STM8S003K3 STM8S003F3 Figure 36: Typical NRST pull-up current vs V The reset network shown in the following figure protects the device against parasitic resets. The user must ensure that the level on the NRST pin can go below V #unique_55/CD662 For power consumption sensitive applications, the external reset capacitor value can be reduced to limit the charge/discharge current ...
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... Slave mode Master mode Slave mode Slave mode Slave mode Slave mode (after enable edge) Master mode (after enable edge) Slave mode (after enable edge) Master mode (after enable edge) DocID018576 Rev 2 STM8S003K3 STM8S003F3 Min Max Unit 0 8 MHz ( MHz ...
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... STM8S003K3 STM8S003F3 (1) Parameters are given by selecting 10 MHz I/O output frequency. (2) Data characterization in progress. (3) Values based on design simulation and/or characterization results, and not tested in production. (4) Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. ...
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... MS BIN t h(MI OUT t v(MO) 2 Table 43 characteristics Standard mode I (2) Min 4.7 4.0 250 (3) 0 4.0 4.7 DocID018576 Rev 2 STM8S003K3 STM8S003F3 (1) t r(SCK) t f(SCK LSB OUT LSB OUT t h(MO Fast mode I C (2) (2) (2) Max Min Max 1.3 0.6 100 ...
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... STM8S003K3 STM8S003F3 Symbol Parameter t STOP condition setup time su(STO) t STOP to START condition time w(STO:ST A) (bus free) C Capacitive load for each bus line b ( must be at least 8 MHz to achieve max fast I MASTER (2) 2 Data based on standard I (3) The maximum hold time of the start condition has only to be met if the interface does not stretch the ...
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... V =4 MHz ADC MHz ADC MHz ADC MHz ADC depend on programming. Table 45: ADC accuracy with R (2) (2) DocID018576 Rev 2 STM8S003K3 STM8S003F3 Min Typ Max 0.75 0.5 7 3.5 2. max) can be charged/discharged AIN After the end of the sample time t S. < ...
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... STM8S003K3 STM8S003F3 Symbol Parameter |E | Gain error Differential linearity error Integral linearity error L (1) Data based on characterization results, not tested in production. (2) ADC accuracy vs. negative injection current: Injecting negative current on any of the analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input ...
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... MHz ADC MHz ADC ( MHz ADC MHz ADC ( MHz ADC MHz ADC does not affect the ADC accuracy. Figure 42: ADC accuracy characteristics DocID018576 Rev 2 STM8S003K3 STM8S003F3 (1) Typ Max Unit 1.5 2.5 1 0.7 1 0.7 1.5 0.6 1.5 0.8 2 and ΣI in I/O port INJ(PIN) ...
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... STM8S003K3 STM8S003F3 3. End point correlation line E = Total unadjusted error: maximum deviation between the actual and the ideal transfer T curves Offset error: deviation between the first actual transition and the first ideal one Gain error: deviation between the last ideal transition and the last actual one. ...
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... Table 48: EMI data Conditions General Monitored conditions frequency band 0.1 MHz ° MHz LQFP32 package 30 MHz to DocID018576 Rev 2 STM8S003K3 STM8S003F3 = 25 ° MHz A MASTER = 25 ° MHz A MASTER (1) Max f /f HSE CPU 16 MHz/ 16 MHz/ 8 MHz 16 MHz 5 ...
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... STM8S003K3 STM8S003F3 Symbol Parameter SAE EMI level (1) Data based on characterisation results, not tested in production. 9.3.11.4 Absolute maximum ratings (electrical sensitivity) Based on three different tests (ESD, DLU and LU) using specific measurement methods, the product is stressed to determine its performance in terms of electrical sensitivity. For more details, refer to the application note AN1181 ...
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... Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC specifications, that means when a device belongs to class A it exceeds the JEDEC standard. B class strictly covers all the JEDEC criteria (international standard). 88/99 Table 50: Electrical sensitivities Conditions ° °C A DocID018576 Rev 2 STM8S003K3 STM8S003F3 (1) Class A A ...
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... STM8S003K3 STM8S003F3 10 Package information In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK trademark. 10.1 32-pin LQFP package mechanical data 24 25 ...
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... Figure 45: 20-pin, 4.40 mm body, 0.65 mm pitch DocID018576 Rev 2 STM8S003K3 STM8S003F3 (1) inches Min Typ Max 0.2205 0.3465 0.3543 0.3622 0.2677 0.2756 0.2835 0.2205 0.0315 0.0177 0.0236 0.0295 0.0394 0.0° 3.5° ...
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... STM8S003K3 STM8S003F3 Table 52: 20-pin, 4.40 mm body, 0.65 mm pitch mechanical data Dim. mm Min A A1 0.050 A2 0.800 b 0.190 c 0.090 D 6.400 E 6.200 E1 4.300 e L 0.450 L1 k 0.0° aaa (1) Values in inches are converted from mm and rounded to 4 decimal digits inches Typ Max Min 1.200 0.150 0.0020 1.000 1 ...
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... L3 Typ Max 3.000 3.000 0.550 0.600 0.020 0.050 0.152 0.500 0.550 0.600 0.350 0.400 0.150 0.200 0.250 0.300 DocID018576 Rev 2 STM8S003K3 STM8S003F3 ddd 103_A0A5_ME (1) inches Min Typ Max 0.1181 0.1181 0.0197 0.0217 0.0236 0.0000 0.0008 0.0020 0.0060 0.0197 ...
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... STM8S003K3 STM8S003F3 11 Thermal characteristics The maximum chip junction temperature (T Operating conditions. The maximum chip-junction temperature, T the following equation Jmax Amax Where: • the maximum ambient temperature in °C Amax • Θ is the package junction-to-ambient thermal resistance in °C/W JA • the sum of P Dmax • ...
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... Jmax This is within the range of the suffix 6 version parts (-40 < this case, parts must be ordered at least with the temperature range suffix 6. 94/ °C (measured according to JESD51-2) Amax = 0 DocID018576 Rev 2 STM8S003K3 STM8S003F3 : JA < 105 °C). J ...
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... STM8S003K3 STM8S003F3 12 Ordering information Figure 47: STM8S003x value line ordering information scheme 1. TSSOP and UFQFPN package. 2. LQFP package. For a list of available options (e.g. package, packing) and orderable part numbers or for further information on any aspect of this device, please go to www.st.com or contact the ST Sales Office nearest to you ...
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... STM8 development tools are supported by a complete, free software package from STMicroelectronics that includes ST Visual Develop (STVD) IDE and the ST Visual Programmer (STVP) software interface. STVD provides seamless integration of the Cosmic and Raisonance C compilers for STM8, which are available in a free version that outputs Kbytes of code. 96/99 DocID018576 Rev 2 STM8S003K3 STM8S003F3 ...
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... STM8S003K3 STM8S003F3 13.2.1 STM8 toolset STM8 toolset with STVD integrated development environment and STVP programming software is available for free download at www.st.com/mcu. This package includes: ST Visual Develop – Full-featured integrated development environment from ST, featuring • Seamless integration of C and ASM toolsets • ...
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... Revision Changes 1 Initial revision. 2 Added N and t RW Flash program memory and data Updated Table 37: I/O static Updated notes related to V operating conditions. DocID018576 Rev 2 STM8S003K3 STM8S003F3 for data EEPROM in Table 36: RET EEPROM. Table 41: NRST pin characteristics characteristics. in Table 18: General CAP and ...
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... STM8S003K3 STM8S003F3 Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at anytime, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...