ST7232AK2 STMicroelectronics, ST7232AK2 Datasheet - Page 135
ST7232AK2
Manufacturer Part Number
ST7232AK2
Description
8-BIT MCU WITH 8K FLASH/ROM, ADC, 4 TIMERS, SPI, SCI INTERFACE
Manufacturer
STMicroelectronics
Datasheet
1.ST7232AK1.pdf
(157 pages)
Specifications of ST7232AK2
Hdflash Endurance
100 cycles, data retention
Clock Sources
crystal/ceramic resonator oscillators and bypass for external clock
Four Power Saving Modes
Halt, Active-Halt, Wait and Slow
Main Clock Controller With
Real time base, Beep and Clock-out capabilities
Two 16-bit Timers With
2 input captures, 2 output compares, PWM and pulse generator modes
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12.11 COMMUNICATION INTERFACE CHARACTERISTICS
12.11.1 SPI - Serial Peripheral Interface
Subject to general operating conditions for V
design simulation and/or characterisation results, not tested in production.
When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave
mode) has its alternate function capability released. In this case, the pin status depends on the I/O port
configuration. Refer to I/O port characteristics for more details on the input/output alternate function char-
acteristics (SS, SCK, MOSI, MISO).
Figure 76. SPI Slave Timing Diagram with CPHA=0
Notes:
1. Measurement points are done at CMOS levels: 0.3xV
Symbol
1/t
t
t
w(SCKH)
w(SCKL)
t
t
t
t
t
t
t
t
dis(SO)
t
t
t
t
r(SCK)
su(SS)
f(SCK)
t
su(MI)
t
v(MO)
h(MO)
f
su(SI)
a(SO)
v(SO)
h(SO)
MISO
MOSI
h(SS)
h(MI)
c(SCK)
h(SI)
SCK
SS
CPHA=0
CPOL=0
CPHA=0
CPOL=1
OUTPUT
INPUT
INPUT
SPI clock frequency
SPI clock rise and fall time
SS setup time
SS hold time
SCK high and low time
Data input setup time
Data input hold time
Data output access time
Data output disable time
Data output valid time
Data output hold time
Data output valid time
Data output hold time
see note 2
t
a(SO)
t
su(SS)
t
su(SI)
Parameter
t
t
MSB IN
w(SCKH)
w(SCKL)
MSB OUT
t
t
h(SI)
c(SCK)
DD
t
v(SO)
, f
DD
CPU
Slave
Master
Slave
Slave
Slave
Master
Slave
Master
Slave
Master
Slave
Slave
Slave (after enable edge)
Master (before capture edge)
BIT6 OUT
and 0.7xV
, and T
1)
Conditions
A
DD
unless otherwise specified. Data based on
BIT1 IN
.
t
f
f
h(SO)
CPU
CPU
=8MHz
=8MHz
t
t
r(SCK)
f(SCK)
f
CPU
LSB IN
0.0625
see I/O port pin description
0.25
0.25
Min
120
120
100
100
100
100
100
90
LSB OUT
0
0
0
/128
t
h(SS)
f
f
CPU
CPU
Max
120
240
90
2
4
/4
/2
ST7232A
t
dis(SO)
135/157
Unit
t
MHz
CPU
ns
note 2
see
1
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