ST7232AK2-Auto STMicroelectronics, ST7232AK2-Auto Datasheet - Page 128

• Manufacturer Part Number: ST7232AK2-Auto
• Description: 8-bit MCU for automotive, 16 Kbyte Flash, 10-bit ADC, 4 timers, SPI, SCI
• Manufacturer: STMicroelectronics

Specifications of ST7232AK2-Auto

• Hdflash Endurance: 100 cycles, data retention
• Clock Sources: crystal/ceramic resonator oscillators and bypass for external clock
• Four Power Saving Modes: halt, active halt, wait and slow
• Main Clock Controller With: real time base, beep and clock-out capabilities
• Two 16-bit Timers With: 2 input captures, 2 output compares, PWM and pulse generator modes

On-chip peripherals
Note:
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Table 44.
1. Legend: SB = start bit, STB = stop bit, PB = parity bit.
In case of wake up by an address mark, the MSB bit of the data is taken into account and
not the parity bit
Even parity
The parity bit is calculated to obtain an even number of ‘1s’ inside the frame made of the 7
or 8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit.
Example, data = 00110101; 4 bits set
Odd parity
The parity bit is calculated to obtain an odd number of ‘1s’ inside the frame made of the 7 or
8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit.
Example, data = 00110101; 4 bits set
Transmission mode
If the PCE bit is set then the MSB bit of the data written in the data register is not transmitted
but is changed by the parity bit.
Reception mode
If the PCE bit is set then the interface checks if the received data byte has an even number
of ‘1s’ if even parity is selected (PS = 0) or an odd number of ‘1s’ if odd parity is selected
(PS = 1). If the parity check fails, the PE flag is set in the SCISR register and an interrupt is
generated if PIE is set in the SCICR1 register.
SCI clock tolerance
During reception, each bit is sampled 16 times. The majority of the 8th, 9th and 10th
samples is considered as the bit value. For a valid bit detection, all the three samples should
have the same value otherwise the noise flag (NF) is set. For example: if the 8th, 9th and
10th samples are 0, 1 and 1 respectively, then the bit value is ‘1’, but the noise flag bit is set
because the three samples values are not the same.
Consequently, the bit length must be long enough so that the 8th, 9th and 10th samples
have the desired bit value. This means the clock frequency should not vary more than 6/16
(37.5%) within one bit. The sampling clock is resynchronized at each start bit, so that when
receiving 10 bits (one start bit, 1 data byte, 1 stop bit), the clock deviation must not exceed
3.75%.
M bit
0
0
1
1
Frame formats
PCE bit
0
1
0
1
(1)
SCI frame
| SB | 8 bit data | STB |
| SB | 7-bit data | PB | STB |
| SB | 9-bit data | STB |
| SB | 8-bit data PB | STB |
=>
=>
parity bit is 1 if odd parity is selected (PS bit = 1).
parity bit is 0 if even parity is selected (PS bit = 0).
ST7232Axx-Auto