DS1250Y Maxim, DS1250Y Datasheet - Page 2

no-image

DS1250Y

Manufacturer Part Number
DS1250Y
Description
The DS1250 4096k Nonvolatile SRAMs are 4,194,304-bit, fully static, nonvolatile SRAMs organized as 524,288 words by 8 bits
Manufacturer
Maxim
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DS1250Y
Manufacturer:
SIL
Quantity:
650
Part Number:
DS1250Y-070ET
Manufacturer:
DALLAS
Quantity:
119
Part Number:
DS1250Y-070ET
Manufacturer:
MAXIM
Quantity:
1 798
Part Number:
DS1250Y-100
Manufacturer:
DALLAS
Quantity:
1 690
Part Number:
DS1250Y-100
Manufacturer:
DALLAS
Quantity:
20 000
Part Number:
DS1250Y-70
Manufacturer:
DALLAS
Quantity:
110
Part Number:
DS1250Y-70
Manufacturer:
DALLAS
Quantity:
20 000
Part Number:
DS1250Y-70
Quantity:
29
Part Number:
DS1250Y-70+
Manufacturer:
Maxim Integrated Products
Quantity:
135
Part Number:
DS1250Y-70IND
Manufacturer:
DALLAS
Quantity:
20 000
Part Number:
DS1250Y-70IND+
Manufacturer:
DALLAS
Quantity:
20 000
Company:
Part Number:
DS1250Y-70IND+
Quantity:
1 000
DESCRIPTION
The DS1250 4096k Nonvolatile SRAMs are 4,194,304-bit, fully static, nonvolatile SRAMs organized as
524,288 words by 8 bits. Each complete NV SRAM has a self-contained lithium energy source and
control circuitry which constantly monitors V
occurs, the lithium energy source is automatically switched on and write protection is unconditionally
enabled to prevent data corruption. DIP-package DS1250 devices can be used in place of existing 512k x
8 static RAMs directly conforming to the popular byte-wide 32-pin DIP standard. DS1250 devices in the
PowerCap Module package are directly surface mountable and are normally paired with a DS9034PC
PowerCap to form a complete Nonvolatile SRAM module. There is no limit on the number of write
cycles that can be executed and no additional support circuitry is required for microprocessor interfacing.
READ MODE
The DS1250 executes a read cycle whenever
and
A
data output drivers within t
then data access must be measured from the later-occurring signal (
is either t
WRITE MODE
The DS1250 executes a write cycle whenever the
inputs are stable. The later-occurring falling edge of
The write cycle is terminated by the earlier rising edge of
valid throughout the write cycle.
before another cycle can be initiated. The
cycles to avoid bus contention. However, if the output drivers are enabled (
will disable the outputs in t
DATA RETENTION MODE
The DS1250AB provides full functional capability for V
4.5 volts. The DS1250Y provides full functional capability for V
protects by 4.25 volts. Data is maintained in the absence of V
The nonvolatile static RAMs constantly monitor V
automatically write protect themselves, all inputs become “don’t care,” and all outputs become high-
impedance. As V
energy source to RAM to retain data. During power-up, when V
the power switching circuit connects external V
Normal RAM operation can resume after V
DS1250Y.
FRESHNESS SEAL
Each DS1250 device is shipped from Maxim with its lithium energy source disconnected, guaranteeing
full energy capacity. When V
is enabled for battery back-up operation.
CE
18
) defines which of the 524,288 bytes of data is to be accessed. Valid data will be available to the eight
and
OE
(Output Enable) are active (low). The unique address specified by the 19 address inputs (A
OE
CO
for
(Output Enable) access times are also satisfied. If
CE
CC
or t
falls below approximately 3.0 volts, a power switching circuit connects the lithium
OE
for
ODW
ACC
CC
OE
from its falling edge.
(Access Time) after the last address input signal is stable, providing that
is first applied at a level greater than 4.25 volts, the lithium energy source
rather than address access.
WE
must return to the high state for a minimum recovery time (t
OE
CC
CC
WE
exceeds 4.75 volts for the DS1250AB and 4.5 volts for the
control signal should be kept inactive (high) during write
for an out-of-tolerance condition. When such a condition
CC
(Write Enable) is inactive (high) and
CC
to RAM and disconnects the lithium energy source.
2 of 10
CE
WE
. Should the supply voltage decay, the NV SRAMs
or WE will determine the start of the write cycle.
CC
and
CE
greater than 4.75 volts and write protects by
CC
CE
OE
or
without any additional support circuitry.
CC
signals are active (low) after address
and
CE
WE
rises above approximately 3.0 volts,
CC
or
. All address inputs must be kept
CE
greater than 4.5 volts and write
OE
access times are not satisfied,
CE
) and the limiting parameter
and
OE
CE
active) then
(Chip Enable)
DS1250Y/AB
WE
WR
0
)
-

Related parts for DS1250Y