DS2406 Maxim, DS2406 Datasheet

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DS2406

Manufacturer Part Number
DS2406
Description
The DS2406 Dual Addressable Switch Plus Memory offers a simple way to remotely control a pair of open drain transistors and to monitor the logic level at each transistor's output via the 1-Wire® bus for closed loop control
Manufacturer
Maxim
Datasheet

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FEATURES
Open drain PIO pins are controlled and their
logic level can be determined over 1-Wire
bus for closed-loop control
Replaces and is fully compatible with
DS2407 but no user-programmable power-on
settings and no Hidden Mode
PIO channel A sink capability of 50mA at
0.4V with soft turn-on; channel B 8mA at
0.4V
Maximum operating voltage of 13V at
PIO-A, 6.5V at PIO-B
1024 bits user-programmable OTP EPROM
User-programmable status memory to
control the device
Multiple DS2406’s can be identified on a
common 1-Wire bus and be turned on or off
independently of other devices on the bus
Unique, factory-lasered and tested 64-bit
registration number (8-bit family code +
48-bit serial number + 8-bit CRC tester)
assures error-free selection and absolute
identity because no two parts are alike
On-chip CRC16 generator allows detection
of data transfer errors
Built-in multidrop controller ensures
compatibility with other 1-Wire net products
Reduces control, address, data, programming
and power to a single data pin
Directly connects to a single port pin of a
microprocessor and communicates at up to
15.4 kbits/s
Supports Conditional Search with user-
selectable condition
V
the device (TSOC package only)
1-Wire communication operates over a wide
voltage range of 2.8V to 6.0V from -40°C to
+85°C
Low cost TO-92 and 6-pin TSOC packages
cc
bondout for optional external supply to
®
1 of 32
PIN ASSIGNMENT
PIN DESCRIPTION
ORDERING INFORMATION
DS2406+
DS2406+T&R
DS2406P+
DS2406P+T&R
+ Indicates lead-free compliance.
Pin 1
Pin 2
Pin 3
Pin 4
Pin 5
Pin 6
Dual Addressable Switch
DALLAS
DS2406
1
1
TO-92
2
2 3
Ground
3
TO-92
PIO-A
Data
---
---
---
BOTTOM VIEW
TO-92 Package
TO-92 Package, Tape & Reel
6-pin TSOC Package
TSOC Package, Tape & Reel
Plus 1Kb Memory
6-PIN TSOC PACKAGE
See Mech. Drawings
1
2
3
SIDE VIEW
TOP VIEW
Section
Ground
TSOC
PIO-A
PIO-B
Data
NC
V
6
5
4
cc
DS2406
033109

Related parts for DS2406

DS2406 Summary of contents

Page 1

... PIO-A, 6.5V at PIO-B 1024 bits user-programmable OTP EPROM User-programmable status memory to control the device Multiple DS2406’s can be identified on a common 1-Wire bus and be turned on or off independently of other devices on the bus Unique, factory-lasered and tested 64-bit registration number (8-bit family code + ...

Page 2

... ADDRESSABLE SWITCH DESCRIPTION The DS2406 Dual Addressable Switch Plus Memory offers a simple way to remotely control a pair of open drain transistors and to monitor the logic level at each transistor’s output via the 1-Wire bus for closed loop control. Each DS2406 has its own 64-bit ROM registration number that is factory lasered into the chip to provide a guaranteed unique identity for absolute traceability. The device’ ...

Page 3

... The block diagram in Figure 1 shows the relationships between the major control and memory sections of the DS2406. The device has four major data components: 64-bit lasered ROM, 1024 bits of EPROM data memory, status memory, and the PIO-control block. The hierarchical structure of the 1-Wire protocol is shown in Figure 2 ...

Page 4

... LASERED ROM Each DS2406 contains a unique ROM code that is 64 bits long. The first 8 bits are a 1-Wire family code. The next 48 bits are a unique serial number. The last 8 bits are a CRC of the first 56 bits. (See Figure 3). ...

Page 5

... Data is first written to the scratchpad and then verified by reading a 16-bit CRC from the DS2406 that confirms proper receipt of the data and address. This process ensures data integrity when programming the memory. If the buffer contents are correct, the bus master should transmit a programming pulse (EPROM dummy byte FFh (RAM) to transfer the data from the scratchpad to the addressed memory location ...

Page 6

... Match ROM command followed by the correct device ROM code. Conversely, a device that does respond to a Read ROM command with family code 12h can only be a DS2406 if its Status Memory location 6 reads 00h. ...

Page 7

... With every subsequent read data time slot the bus master receives data from the DS2406 starting at the initial address and continuing until the end of the 1024-bits data field is reached or until a Reset Pulse is issued. If reading occurs through the end of memory space, the bus master may issue sixteen additional read time slots and the DS2406 will respond with a 16-bit CRC of the command, address bytes and all data bytes read from the initial starting byte through the last byte of memory ...

Page 8

... If the CRC received by the bus master is correct, the bus master issues read time slots and receives data from the DS2406 starting at the initial address and continuing until the end of a 32-byte page is reached. At that point the bus master will send sixteen additional read time slots and receive a 16- bit CRC that is the result of shifting into the CRC generator all of the data bytes from the initial starting byte to the last byte of the current page ...

Page 9

... As the DS2406 receives this byte of data into the scratchpad, it also shifts the data into the CRC generator that has been preloaded with the current address and the result is a 16-bit CRC of the new data byte and the new address ...

Page 10

... Bus Master TX Reset Pulse S DS2406 TX Presence Pulse A5h N Extended Rd. Memory ? Y Bus Master TX TA1(T7:T0), TA2 (T15:T8) DS2406 sets Memory Address = (T15:T0) Bus Master RX Redirection Byte N CRC Correct ? Y Bus Master RX Data from Data Memory Y DS2406 Master increments TX Reset ? Address N Counter ...

Page 11

... Address, Data (1st pass); CRC16 of Address, Data (subsequent passes) N CRC Correct ? Y N Address < Bus Master TX Program Pulse DS2406 copies Scratch- pad to Status EPROM Bus Master RX Byte from Status EPROM N EPROM Byte Correct ? Y DS2406 increments Address Counter DS2406 loads new Address into CRC Generator ...

Page 12

... Memory Function Flow Chart (continued) Figure 7 From Figure 7 2nd Part AAh Read Status ? Bus Master TX TA1(T7:T0), TA2 (T15:T8) DS2406 sets Status Address = (T15:T0) Bus Master RX Data from Status Memory DS2406 Master increments TX Reset ? Address Counter N End of Status Mem. ? Master TX Reset ? Bus Master RX CRC16 of ...

Page 13

... The address bits T3:T6 remain unchanged and will be ignored by the address decoder of the DS2406. Only if one or more of the address bits T8:T15 is set, the bus master will be able to discover an error condition based on the CRC16 that is calculated by the DS2406 ...

Page 14

... PIOs can never change their status at the same time. When writing in the synchronous mode, both channels operate together. After the new values for both channels have arrived at the DS2406 the change of status at both channels occurs with the same timing relations as for communication with one channel ...

Page 15

... DS2406 for channel access. It does not affect reading from or writing to the memory sections of the DS2406. The CRC control bits (bit 0 and bit 1) can be set to create and protect data packets that have the size of 8 bytes or 32 bytes. If desired, the device can safeguard even single bytes by a 16-bit CRC ...

Page 16

... If channel B is available, bit 6 of the Channel Info Byte reads 1. For 1-channel versions of the DS2406, the PIO B sensed level, channel flip-flop value, and activity latch value should be ignored. Without an external supply, the supply indication bit (bit 7) reads 0. As long as the voltage applied to the V pin is high enough to operate the device this bit will read 1 ...

Page 17

... To facilitate this, each device attached to the 1-Wire bus must have an open drain or 3-state outputs. The 1-Wire port of the DS2406 is open drain with an internal circuit equivalent to that shown in Figure 11. Typical bus master ports are shown in Figure 12 bi-directional pin is not available, separate output and input pins can be tied together ...

Page 18

... DS2406 EQUIVALENT CIRCUIT Figure 11 1-Wire Interface DATA 5 µA Typ. MOSFET Ground BUS MASTER CIRCUIT Figure 12 A) Open Drain V DD BUS MASTER DS5000 OR 8051- EQUIVALENT Open Drain Port Pin RX TX The interface is reduced to the B) Standard TTL V DD BUS MASTER TTL-Equivalent Port Pins ...

Page 19

... The presence pulse lets the bus master know that the DS2406 is on the bus and is ready to operate. For more details, see the “1-Wire Signaling” section. ...

Page 20

... Bus Master TX Memory Function Command ECh CCh N N Conditional Skip ROM Search Command ? Y Condition Fulfilled ? DS2406 TX Bit 0 DS2406 TX Bit 0 Master TX Bit 0 Bit 0 Match ? DS2406 TX Bit 1 DS2406 TX Bit 1 Master TX Bit 1 Bit 1 Match ? DS2406 TX Bit 63 DS2406 TX Bit 63 Master TX Bit 63 Bit 63 Match ? Vertical Spare N ? ...

Page 21

Conditional Search ROM [ECh] The Conditional Search ROM command operates similarly to the Search ROM command except that only devices fulfilling the specified condition will participate in the search. This command provides an efficient means for the bus master to ...

Page 22

... Access command if the ALR bit of the Channel Control Byte 1 is set. The activity latch is automatically cleared when the DS2406 powers up. In order to use the activity latch the output transistor of the selected channel should be non-conducting. Otherwise signals applied to the PIO pin will be shorted to ground by the low impedance of the output transistor ...

Page 23

... For a read data time slot “0” transmitted, the delay circuit determines how long the DS2406 will hold the data line low. If the data bit is a “1”, the DS2406 will not hold the data line low at all. ...

Page 24

... Sampling Window t LOW1 15µs 60µs 60 µs ≤ t < 120 µs SLOT 1 µs ≤ t < 15 µs LOW1 ∞ 5 µs ≤ t < REC t SLOT DS2406 Sampling Window 15µs 60µs t LOW0 60 µs ≤ t < t < 120 µs LOW0 SLOT ∞ 5 µs ≤ t < REC ...

Page 25

... DS2406. This programming voltage (Figure 16) should be applied for 480µs, after which the bus master should return the data line to the idle high state. Note that due to the high voltage programming requirements for any 1-Wire EPROM device not possible to multi-drop non-EPROM based 1-Wire devices with the DS2406 during programming ...

Page 26

... CRC is X been read without error the bus master can compute the CRC value from the first 56 bits of the 64-bit ROM and compare it to the value read from the DS2406. This 8-bit CRC is received in the true form (non-inverted) when reading the ROM. ...

Page 27

... The comparison of CRC values and decision to continue with an operation are determined entirely by the bus master. There is no circuitry on the DS2406 that prevents a command sequence from proceeding if a CRC error occurs. For more details on generating CRC values including example implementations in both hardware and software, see Application Note 27 ...

Page 28

... Soldering Temperature * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. DC ELECTRICAL CHARACTERISTICS DATA PIN ...

Page 29

CAPACITANCES PARAMETER Capacitance DATA Pin Capacitance PIO-A Pin Capacitance PIO-B Pin Capacitance V Pin CC AC ELECTRICAL CHARACTERISTICS PARAMETER Time Slot Write 1 Low Time Write 0 Low Time Read Low Time Read Data Valid Release Time Read Data Setup ...

Page 30

... If the current at PIO-A reaches 200mA the gate voltage of the output transistor will be reduced to limit the sink current to 200mA. The user-supplied circuitry should limit the current flow through the PIO-transistor to no more than 100mA. Otherwise the DS2406 may be damaged. 8. PIO-A has a controlled turn-on output. The indicated currents are DC values higher the sink current typically reaches 80% of its DC value 1 µ ...

Page 31

... An additional reset or communication sequence cannot begin until the reset high time has expired. 15. The Reset Low Time (t RSTL otherwise, it could mask or conceal interrupt pulses. 16. The accumulative duration of the programming pulses for each address must not exceed 5ms. ) should be restricted to a maximum of 960μs to allow interrupt signaling ...

Page 32

... Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product. No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any MAXIM is a registered trademark of Maxim Integrated Products, Inc ...

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