DS2406 Maxim, DS2406 Datasheet - Page 5

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DS2406

Manufacturer Part Number
DS2406
Description
The DS2406 Dual Addressable Switch Plus Memory offers a simple way to remotely control a pair of open drain transistors and to monitor the logic level at each transistor's output via the 1-Wire® bus for closed loop control
Manufacturer
Maxim
Datasheet

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MEMORY MAP
The DS2406 has two memory sections, called data memory and status memory. The data memory
consists of 1024 bits of one-time programmable EPROM organized as 4 pages of 32 bytes each. The
address range of the device’s status memory is 8 bytes. The first seven bytes of status memory (addresses
0 to 6) are implemented as EPROM. The eighth byte (address 7) consists of static RAM. The complete
memory map is shown in Figure 5. The 8-bit scratchpad is an additional register that acts as a buffer when
writing the memory. Data is first written to the scratchpad and then verified by reading a 16-bit CRC
from the DS2406 that confirms proper receipt of the data and address. This process ensures data integrity
when programming the memory. If the buffer contents are correct, the bus master should transmit a
programming pulse (EPROM) or a dummy byte FFh (RAM) to transfer the data from the scratchpad to
the addressed memory location. The details for reading and programming the DS2406 are given in the
Memory Function Commands section.
DS2406 MEMORY MAP Figure 5
DS2406 STATUS MEMORY MAP Figure 6
0 (EPROM)
1 (EPROM)
2 (EPROM)
3 (EPROM)
4 (EPROM)
5 (EPROM)
6 (EPROM)
7 (SRAM)
ADDRESS
EPROM
Memory
8 Bytes
1K-Bit
Status
(read only)
Indication
Supply
BIT 7
BM3
1
1
1
1
Valid Device
Page #
(SRAM)
Settings
0
1
2
3
Flip-flop
Channel
PIO-B
BIT 6
BM2
1
1
1
1
Address Range
0000h to 001Fh
0020h to 003Fh
0040h to 005Fh
0060h to 007Fh
00
Flip-flop
Channel
PIO-A
BIT 5
BM1
Test Byte
1
1
1
1
Factory
Don’t care, always reads 00
EPROM Factory Test byte
8-Bit Scratchpad
5 of 32
Channel
BIT 4
Select
CSS4
BM0
1
1
1
1
Redirection
Bytes
32-Byte final storage Data Memory
32-Byte final storage Data Memory
32-Byte final storage Data Memory
32-Byte final storage Data Memory
Channel
BIT 3
Select
CSS3
WP3
1
1
1
1
Used Pages
Bitmap of
Description
Source
BIT 2
Select
CSS2
WP2
1
1
1
1
Redir. 0
Redir. 1
Redir 2
Redir 3
Source
BIT 1
Select
CSS1
Write-Protect
WP1
Bits Data
Memory
Redir. 0
Redir. 1
Polarity
Redir 2
Redir 3
BIT 0
CSS0
WP0

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