DS2408 Maxim, DS2408 Datasheet - Page 9

• Manufacturer Part Number: DS2408
• Description: The DS2408 is an 8-channel, programmable I/O 1-Wire® chip
• Manufacturer: Maxim

PIO Logic-State Register
The logic state of the PIO pins can be obtained by reading this register using the Read PIO Registers
command. Reading this register does not generate a signal at the RSTZ pin, even if it is configured as
PIO Logic State Register Bitmap
This register is read-only. Each bit is associated with the pin of the respective PIO channel as shown in
Figure 6. The data in this register is sampled at the last (most significant) bit of the byte that proceeds
reading the first (least significant) bit of this register. See the Read PIO Registers command description
for details.
PIO Output Latch State Register
The data in this register represents the latest data written to the PIO through the Channel-access Write
command. This register is read using the Read PIO Registers command. Reading this register does not
generate a signal at the RSTZ pin, even if it is configured as
description for details on
hit.
PIO Output Latch State Register Bitmap
This register is read-only. Each bit is associated with the output latch of the respective PIO channel as
shown in Figure 6.
The flip-flops of this register will power up in a random state. If the chip has to power up with all PIO
channels off, a LOW pulse must be generated on the RSTZ pin, e.g., by means of an open-drain CPU
supervisor chip (see Figure 20). When using an RC circuit to generate the power-on reset, make sure that
RSTZ is NOT configured as strobe output (ROS bit in control/status register 008Dh needs to be 0).
PIO Activity Latch State Register
The data in this register represents the current state of the PIO activity latches. This register is read using
the Read PIO Registers command. Reading this register does not generate a signal at the RSTZ pin, even
if it is configured as
PIO Activity Latch State Register Bitmap
This register is read-only. Each bit is associated with the activity latch of the respective PIO channel as
shown in Figure 6. This register is cleared to 00h by a power-on reset, by a low pulse on the RSTZ pin
(only if RSTZ is configured as
command.
STRB
ADDR
ADDR
ADDR
008Ah
0088h
0089h
. See the Channel-Access commands description for details on
PL7
AL7
P7
b7
b7
b7
STRB
PL6
AL6
P6
b6
b6
b6
STRB
. See the Channel-access commands description for details on
PL5
AL5
P5
b5
b5
b5
. This register is not affected if the device reinitializes itself after an ESD
RST
input), or by successful execution of the Reset Activity Latches
PL4
AL4
P4
b4
b4
b4
PL3
AL3
P3
b3
b3
b3
9 of 39
PL2
AL2
P2
b2
b2
b2
STRB
PL1
AL1
P1
b1
b1
b1
. See the Channel-access commands
STRB
.
PL0
AL0
P0
b0
b0
b0
STRB
.
DS2408