DS2431 Maxim, DS2431 Datasheet - Page 3

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DS2431

Manufacturer Part Number
DS2431
Description
The DS2431 is a 1024-bit, 1-Wire® EEPROM chip organized as four memory pages of 256 bits each
Manufacturer
Maxim
Datasheet

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ELECTRICAL CHARACTERISTICS (continued)
(T
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10: After V
Note 11: The I-V characteristic is linear for voltages less than 1V.
Note 12: Applies to a single device attached to a 1-Wire line.
Note 13: The earliest recognition of a negative edge is possible at t
Note 14: Defines maximum possible bit rate. Equal to t
Note 15: Interval after t
Note 16: Numbers in bold are not in compliance with legacy 1-Wire product standards. See the Comparison Table .
Note 17: ε in Figure 11 represents the time required for the pullup circuitry to pull the voltage on IO up from V
Note 18: δ in Figure 11 represents the time required for the pullup circuitry to pull the voltage on IO up from V
IO PIN: 1-Wire WRITE
Write-Zero Low Time
(Notes 2, 16, 17)
Write-One Low Time
(Notes 2, 17)
IO PIN: 1-Wire READ
Read Low Time
(Notes 2, 18)
Read Sample Time
(Notes 2, 18)
EEPROM
Programming Current
Programming Time
Write/Erase Cycles (Endurance)
(Notes 22, 23)
Data Retention
(Notes 24, 25, 26)
A
= -40°C to +85°C.) (Note 1)
PARAMETER
Limits are 100% production tested at T
evant supply voltage range are guaranteed by design and characterization. Typical values are not guaranteed.
System requirement.
Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery times.
The specified value here applies to systems with only one device and with the minimum 1-Wire recovery times. For more
heavily loaded systems, an active pullup such as that found in the DS2482-x00, DS2480B, or DS2490 may be required.
Maximum value represents the internal parasite capacitance when V
up the data line, 2.5µs after V
Guaranteed by design, characterization, and/or simulation only. Not production tested.
V
capacitive loading on IO. Lower V
V
Voltage below which, during a falling edge on IO, a logic 0 is detected.
The voltage on IO must be less than or equal to V
Voltage above which, during a rising edge on IO, a logic 1 is detected.
Minimum limit is t
maximum duration for the master to pull the line low is t
threshold of the bus master. The actual maximum duration for the master to pull the line low is t
TL
TL
, V
, V
TH
TH
TH
, and V
, and V
is crossed during a rising edge on IO, the voltage on IO must drop by at least V
_______________________________________________________________________________________
RSTL
HY
HY
PDHMAX
.
are a function of the internal supply voltage, which is a function of V
during which a bus master is guaranteed to sample a logic 0 on IO if there is a DS2431 present.
; maximum limit is t
SYMBOL
I
t
t
PROG
PROG
t
t
N
PUP
MSR
t
W0L
W1L
t
DR
RL
CY
has been applied, the parasite capacitance does not affect normal communications.
PUP
, higher R
A
Standard speed
Overdrive speed, V
Overdrive speed
Standard speed
Overdrive speed
Standard speed
Overdrive speed
Standard speed
Overdrive speed
(Notes 5, 19)
(Notes 20, 21)
At +25°C
At +85°C (worst case)
At +85°C (worst case)
= +25°C and/or T
PDHMIN
W0LMIN
PUP
ILMAX
, shorter t
+ t
1024-Bit, 1-Wire EEPROM
+ t
CONDITIONS
PDLMIN
W1LMAX
at all times the master is driving IO to a logic 0 level.
RECMIN
REH
A
PUP
= +85°C. Limits over the operating temperature range and rel-
REC
.
after V
> 4.5V
.
+ t
, and heavier capacitive loading all lead to lower values of
F
- ε and t
PUP
TH
has been reached on the preceding rising edge.
is first applied. If a 2.2kΩ resistor is used to pull
W0LMAX
+ t
t
t
RL
RL
200k
PUP
MIN
50k
F
60
40
5
6
1
1
5
1
HY
- ε, respectively.
+
+
, R
to be detected as logic 0.
PUP
RLMAX
TYP
, 1-Wire timing, and
IL
IL
+ t
to V
to the input-high
F
15 -
MAX
.
15.5
15.5
2 -
TH
120
0.8
15
15
10
2
2
. The actual
UNITS
Years
mA
ms
μs
μs
μs
μs
3

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