DS2460 Maxim, DS2460 Datasheet - Page 4

• Manufacturer Part Number: DS2460
• Description: The DS2460 SHA-1 Coprocessor with EEPROM is a hardware implementation of the ISO/IEC 10118-3 Secure Hash Algorithm (SHA-1), eliminating the need to develop software to perform the complex SHA computation required for authenticating SHA devices and fo
• Manufacturer: Maxim

Figure 1. Block Diagram
DETAILED REGISTER DESCRIPTION
For this section (including Figure 3) please refer to the full version of the data sheet.
DEVICE OPERATION
The typical use of the DS2460 in an application involves writing, reading, running the SHA-1 engine, transferring
secrets and comparing MACs. All these activities are controlled through the I²C serial interface.
I²C Serial Communication Interface
General Characteristics
The I²C bus uses a data line (SDA) plus a clock signal (SCL) for communication. Both SDA and SCL are bidirec-
tional lines, connected to a positive supply voltage through a pullup resistor. When there is no communication, both
lines are HIGH. The output stages of devices connected to the bus must have an open-drain or open-collector to
perform the wired-AND function. Data on the I²C bus can be transferred at rates of up to 100kbps in the Standard-
mode, up to 400kbps in the Fast-mode. The DS2460 works in both modes.
A device that sends data on the bus is defined as a transmitter, and a device receiving data as a receiver. The
device that controls the communication is called a “master.” The devices that are controlled by the master are
“slaves.” To be individually accessed, each device must have a slave address that does not conflict with other
devices on the bus.
Data transfers may be initiated only when the bus is not busy. The master generates the serial clock (SCL),
controls the bus access, generates the START and STOP conditions, and determines the number of data bytes
transferred between START and STOP (Figure 4). Data is transferred in bytes with the most significant bit being
transmitted first. After each byte follows an acknowledge bit to allow synchronization between master and slave.
SCL
SDA
ADx
64-bit Unique
Function
Number
Control
2-wire
Command Buffer
8-Byte EEPROM
Engine Control
4 of 9
Write Buffer
and SHA-1
112-Byte User
64-Byte Input
MAC Output
E-Secret1
E-Secret2
E-Secret3
EEPROM
S-Secret
Engine
SHA-1
Buffer
Buffer