DS2460 Maxim, DS2460 Datasheet - Page 6

• Manufacturer Part Number: DS2460
• Description: The DS2460 SHA-1 Coprocessor with EEPROM is a hardware implementation of the ISO/IEC 10118-3 Secure Hash Algorithm (SHA-1), eliminating the need to develop software to perform the complex SHA computation required for authenticating SHA devices and fo
• Manufacturer: Maxim

Repeated START Condition
Repeated starts are commonly used for read accesses to select a specific data source or address to read from.
The master can use a repeated START condition at the end of a data transfer to immediately initiate a new data
transfer following the current one. A repeated START condition is generated the same way as a normal START
condition, but without leaving the bus idle after a STOP condition.
Data Valid
With the exception of the START and STOP condition, transitions of SDA may occur only during the LOW state of
SCL. The data on SDA must remain valid and unchanged during the entire high pulse of SCL plus the required
setup and hold time (t
There is one clock pulse per bit of data. Data is shifted into the receiving device during the rising edge of the SCL
pulse.
When finished with writing, the master must release the SDA line for a sufficient amount of setup time (minimum
t
SDA at the falling edge of the previous SCL pulse and the data bit is valid at the rising edge of the current SCL
pulse. The master generates all SCL clock pulses, including those needed to read from a slave.
Acknowledge
Usually, a receiving device, when addressed, is obliged to generate an acknowledge after the receipt of each byte.
The master must generate a clock pulse that is associated with this acknowledge bit. A device that acknowledges
must pull SDA LOW during the acknowledge clock pulse in such a way that SDA is stable LOW during the HIGH
period of the acknowledge-related clock pulse plus the required setup and hold time (t
SCL and t
Not Acknowledged by Slave
A slave device may be unable to receive or transmit data, e.g., because it is busy performing a real-time function,
such as MAC computation or EEPROM write cycle. In this case the slave device will not acknowledge its slave
address and leave the SDA line HIGH.
A slave device that is ready to communicate will acknowledge at least its slave address. However, some time later
the slave may refuse to accept data, e.g., because of an invalid command or access mode, or to signal a non-
matching MAC. In this case the slave device will not acknowledge any of the bytes that it refuses and will leave
SDA HIGH. In either case, after a slave has failed to acknowledge, the master first needs to generate a repeated
START condition or a STOP condition followed by a START condition to begin a new data transfer.
Not Acknowledged by Master
At some time when receiving data, the master must signal an end of data to the slave device. To achieve this, the
master does not acknowledge the last byte that it has received from the slave. In response, the slave releases
SDA, allowing the master to generate the STOP condition.
Figure 6. I²C Timing Diagram
SU:DAT
SCL
SDA
+ t
STOP START
R
SU:DAT
in Figure 6) before the next rising edge of SCL to start reading. The slave shifts out each data bit on
t
BUF
before the rising edge of SCL).
t
HD:DAT
HD:STA
t
LOW
after the falling edge of SCL and t
t
R
t
HD:DAT
t
t
F
HIGH
t
SU:DAT
6 of 9
Repeated
START
SU:DAT
t
SU:STA
t
before the rising edge of SCL, see Figure 6).
HD:STA
NOTE: Timing is referenced
to V
ILMAX
Suppression
Spike
and V
HD:DAT
IHMIN
t
SP
after the falling edge of
.
t
SU:STO