DS2460 Maxim, DS2460 Datasheet - Page 7

• Manufacturer Part Number: DS2460
• Description: The DS2460 SHA-1 Coprocessor with EEPROM is a hardware implementation of the ISO/IEC 10118-3 Secure Hash Algorithm (SHA-1), eliminating the need to develop software to perform the complex SHA computation required for authenticating SHA devices and fo
• Manufacturer: Maxim

Read and Write
This section discusses the read and write behavior of the various registers and the EEPROM. Please refer to the
full data sheet for details.
SHA-1 Engine Control
This section describes the user’s view of the SHA-1 engine and how to operate it. For details refer to the full data
sheet (includes Figures 7 to 9 and Tables 1 and 2).
SHA-1 COMPUTATION ALGORITHM
This description of the SHA computation is adapted from the Secure Hash Standard SHA-1 document that can be
downloaded from the NIST website (www.itl.nist.gov/fipspubs/fip180-1.htm). Further details are found in the full
version of the data sheet.
Application Information
SDA and SCL Pullup Resistors
SDA is an open-drain output on the DS2460 that requires a pullup resistor (Figure 10) to realize high logic levels.
Because the DS2460 uses SCL only as input (no clock stretching) the master can drive SCL either through an
open-drain/collector output with a pullup resistor or a push-pull output.
Figure 10. Application Schematic
Pullup Resistor R
According to the I²C specification, a slave device must be able to sink at least 3mA at a V
condition determines the minimum value of the pullup resistor: R
of 5.5V, the minimum value for the pullup resistor is 1.7k. The "Minimum R
minimum pullup resistor changes with the operating (pull-up) voltage.
For I²C systems, the rise time and fall time are measured from 30% to 70% of the pullup voltage. The maximum
bus capacitance C
maximum resistor value at any given capacitance C
capacitance of 400pF the maximum pullup resistor would be 885.
P
B
Sizing
is 400pF. The maximum rise time must not exceed 300ns. Assuming maximum rise time, the
V
CC
GND
µC
V
CC
SDA
SCL
R
P
B
7 of 9
is calculated as: R
R
P
SDA
SCL
PMIN
GND
V
= (V
CC
AD0
AD1
AD2
CC
- 0.4V)/3mA. With an operating voltage
PMAX
P
" line in Figure 11 shows how the
To additional
2-wire devices
= 300ns/(C
Example
slave
address =
100 0101
B
OL
*ln(7/3)). For a bus
of 0.4V. This DC