DS28CM00 Maxim, DS28CM00 Datasheet - Page 3

• Manufacturer Part Number: DS28CM00
• Description: The DS28CM00 is a low-cost, electronic registration number to provide an absolutely unique identity that can be determined with the industry standard I²C and SMBus&#8482 interface
• Manufacturer: Maxim

Data Hold Time (Notes 9, 10)
Data Setup Time
Setup Time for STOP Condition
Bus Free Time Between a
STOP and START Condition
Capacitive Load for Each Bus
Line
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
PIN DESCRIPTION
OVERVIEW
The DS28CM00 consists of a serial interface which provides access to a unique 64-bit Registration number and a
Control Register, as shown in the block diagram in Figure 1. The device communicates with a host processor
through its SMBus compatible I²C bus interface in standard-mode or in fast-mode. Since the network address of
the DS28CM00 is fixed, exactly one device can reside on a bus segment. The Registration Number and Control
Register are located in a linear 9-byte address space (Figure 2).
PIN
1
2
3
4
5
PARAMETER
NAME
Specifications at -40°C are guaranteed by design and characterization only and not production tested.
All values are referred to V
The maximum specification value is guaranteed by design, not production tested.
Not production tested. Guaranteed by design or characterization.
C
to I
The DS28CM00 does not obstruct the SDA and SCL lines if V
The minimum SCL clock frequency is limited by the bus timeout feature. If the CM bit is 1 AND SCL
stays at the same logic level or SDA stays low for this interval, the DS28CM00 behaves as though it
has sensed a STOP condition.
System Requirement
The DS28CM00 provides a hold time of at least 300ns for the SDA signal (referred to the V
SCL signal) to bridge the undefined region of the falling edge of SCL.
The maximum t
signal.
A Fast-mode I²C-bus device can be used in a standard-mode I²C-bus system, but the requirement
t
period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must
output the next data bit to the SDA line tr max + t
standard-mode I²C-bus specification) before the SCL line is released.
SU:DAT
GND
SDA
N.C.
SCL
V
B
CC
2
= total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times according
C-Bus Specification v2.1 are allowed.
≥ 250ns must then be met. This is automatically the case if the device does not stretch the LOW
Serial interface clock input; must be tied to V
over 1.62V to 5.25V V
Ground supply for the device.
Serial interface bi-directional data line; must be tied to V
tolerant input/output over 1.62V to 5.25V V
Not Connected
Power Supply Input
HD:DAT
has only to be met if the device does not stretch the low period (t
SYMBOL
t
t
t
HD:DAT
SU:DAT
SU:STO
t
BUF
C
IHmin
b
and V
CC
V
V
V
(Notes 8, 11)
(Note 8)
(Note 8)
(Notes 4, 8)
range.
CC
CC
CC
ILmax
≥ 2.7V
≥ 2.0V
< 2.0V
CONDITIONS
levels.
3 of 9
SU:DAT
FUNCTION
CC
= 1000 + 250 = 1250ns (according to the
CC
DS28CM00: I²C/SMBus Silicon Serial Number
range.
through a pullup resistor. 5V tolerant input
CC
is switched off.
MIN
100
0.3
0.3
0.3
0.6
1.3
CC
through a pullup resistor. 5V
TYP
MAX
400
LOW
0.9
1.1
1.7
) of the SCL
IHmin
UNITS
of the
pF
µs
ns
µs
µs