DS28E01-100 Maxim, DS28E01-100 Datasheet - Page 3

• Manufacturer Part Number: DS28E01-100
• Description: The DS28E01-100 combines 1024 bits of EEPROM with challenge-and-response authentication security implemented with the ISO/IEC 10118-3 Secure Hash Algorithm (SHA-1)
• Manufacturer: Maxim

ELECTRICAL CHARACTERISTICS (continued)
(T
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10: After V
Note 11: The I-V characteristic is linear for voltages less than 1V.
Note 12: Applies to a single device attached to a 1-Wire line.
Note 13: The earliest recognition of a negative edge is possible at t
Note 14: Defines maximum possible bit rate. Equal to t
Note 15: Interval after t
Note 16: Numbers in bold are not in compliance with legacy 1-Wire product standards. See the Comparison Table .
IO PIN: 1-Wire WRITE
Write-Zero Low Time
(Notes 2, 16, 17)
Write-One Low Time
(Notes 2, 17)
IO PIN: 1-Wire READ
Read Low Time
(Notes 2, 18)
Read Sample Time
(Notes 2, 18)
EEPROM
Programming Current
Programming Time
Write/Erase Cycles (Endurance)
(Notes 21, 22)
Data Retention
(Notes 23, 24, 25)
SHA-1 ENGINE
Computation Current
Computation Time
(Notes 5, 26)
A
= -40°C to +85°C.) (Note 1)
PARAMETER
Specifications at T
System requirement.
Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery times.
The specified value here applies to systems with only one device and with the minimum 1-Wire recovery times. For more
heavily loaded systems, an active pullup such as that found in the DS2482-x00, DS2480B, or DS2490 may be required.
Maximum value represents the internal parasite capacitance when V
the parasite capacitance does not affect normal communications 2.5µs after V
Guaranteed by design, characterization, and/or simulation only. Not production tested.
V
capacitive loading on IO. Lower V
V
Voltage below which, during a falling edge on IO, a logic 0 is detected.
The voltage on IO must be less than or equal to V
Voltage above which, during a rising edge on IO, a logic 1 is detected.
Minimum limit is t
TL
TL
, V
, V
TH
TH
TH
, and V
, and V
is crossed during a rising edge on IO, the voltage on IO must drop by at least V
_______________________________________________________________________________________
RSTL
HY
HY
PDHMAX
.
ABRIDGED DATA SHEET
A
are a function of the internal supply voltage, which is a function of V
during which a bus master is guaranteed to sample a logic 0 on IO if there is a DS28E01-100 present.
= -40°C are guaranteed by design only and not production tested.
; maximum limit is t
SYMBOL
I
I
t
t
LCSHA
PROG
PROG
t
CSHA
t
t
N
MSR
t
W0L
W1L
t
DR
RL
CY
PUP
1Kb Protected 1-Wire EEPROM
, higher R
Standard speed
Overdrive speed, V
Overdrive speed
Standard speed
Overdrive speed
Standard speed
Overdrive speed
Standard speed
Overdrive speed
(Notes 5, 19)
(Note 20)
At +25°C
At +85°C (worst case)
At +85°C (worst case)
PDHMIN
W0LMIN
PUP
ILMAX
, shorter t
+ t
+ t
CONDITIONS
PDLMIN
at all times the master is driving IO to a logic 0 level.
RECMIN
REH
PUP
Refer to the full data sheet.
REC
.
after V
> 4.5V
.
, and heavier capacitive loading all lead to lower values of
PUP
TH
with SHA-1 Engine
has been reached on the preceding rising edge.
is first applied. If a 2.2kΩ pullup resistor is used,
PUP
has been applied.
t
t
RL
RL
PUP
200k
MIN
50k
60
40
HY
5
6
1
1
5
1
+
+
, R
to be detected as logic 0.
PUP
TYP
, 1-Wire timing, and
15 -
MAX
15.5
15.5
2 -
120
0.8
15
15
10
2
2
UNITS
Years
mA
mA
ms
ms
μs
μs
μs
μs
3