DS80C400 Maxim, DS80C400 Datasheet - Page 40

• Manufacturer Part Number: DS80C400
• Description: The DS80C400 network microcontroller offers the highest integration available in an 8051 device
• Manufacturer: Maxim

TIMED-ACCESS PROTECTION
Selected SFR bits are critical to operation, making it desirable to protect them against an accidental write
operation. The timed-access procedure prevents errant behavior from accidentally altering bits that would seriously
affect microcontroller operation. The timed-access procedure requires that the write of a protected bit be
immediately preceded by the following two instructions:
MOV
MOV
Writing an AAh followed by a 55h to the timed access register (location C7h), opens a three-cycle window that
allows software to modify one of the protected bits. The protected bits are:
MEMORY ARCHITECTURE
The DS80C400 incorporates four internal memory areas:
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Up to 16MB of external code memory can be addressed through a multiplexed or demultiplexed 22-bit address
bus/8-bit data bus through eight available chip enables. Up to 4MB of external data memory can be accessed over
the same address/data buses through peripheral-enable signals. The DS80C400 also permits a 16MB merged
program/data memory map.
WDCON (D8h)
256 Bytes of scratchpad (or direct) RAM
8kB of SRAM for Ethernet MAC transmit/receive buffer memory
1kB of SRAM configurable as various combinations of data memory and stack memory
256 Bytes of RAM reserved for the CAN message centers
64kB embedded ROM firmware
MCON1 (D6h)
MCON2 (D7h)
P5CNT (A2h)
P6CNT (B2h)
P4CNT (92h)
MCON (C6h)
ACON (9Dh)
COR (CEh)
EXIF (91h)
C0C (A3h)
EBS (E5h)
0C7h, #0AAh
0C7h, #55h
SFR
—
—
—
—
—
—
—
—
—
—
—
—
—
MCON1.3–0
MCON2.6–4
MCON2.3–0
P4CNT.5–0
P5CNT.2–0
P6CNT.5–0
MCON.7–6
MCON.3–0
ACON.1–0
WDCON.6
WDCON.3
WDCON.1
WDCON.0
COR.4–3
COR.2–1
MCON.5
EBS.4–0
ACON.5
ACON.4
ACON.3
ACON.2
EXIF.0
COR.7
COR.0
BIT(S)
C0C.3
EBS.7
C0BPR7–C0BPR6
PDCE3–PDCE0
PDCE7–PDCE4
WPR2–WPR0
WPE3–WPE0
COD1–COD0
IDM1–IDM0
AM1–AM0
BS4-BS0
IRDACK
CLKOE
MROM
BROM
NAME
BPME
CRST
WDIF
EWT
RWT
BGS
CAN
POR
FPE
SA
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Bandgap Select
Port 4 Pin Configuration Control Bits
Merge ROM
Breakpoint Mode Enable
By-Pass ROM
Stack Address Mode
Address Mode Select Bits
Port 5 Pin Configuration Control Bits
CAN 0 Reset
Port 6 Pin Configuration Control Bits
Internal Memory Configuration Bits
CMA Data Memory Assignment
Program/Data-Chip Enables
IRDA Clock-Output Enable
CAN 0 Baud Rate Prescale Bits
CAN Clock-Output Divide Bits
CAN Clock-Output Enable
Program/Data Chip Enable
Write-Protect Range Bits
Write-Protect Enable Bits
Power-On Reset Flag
Watchdog Interrupt Flag
Watchdog Reset Enable
Reset Watchdog Timer
Flush Filter Failed-Packet Enable
Buffer Size Configuration Bits
FUNCTION