DS80C400 Maxim, DS80C400 Datasheet - Page 47

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DS80C400

Manufacturer Part Number
DS80C400
Description
The DS80C400 network microcontroller offers the highest integration available in an 8051 device
Manufacturer
Maxim
Datasheet

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Table 9. Data Memory Cycle Stretch Values
Note 1: All internal MOVX operations execute at the 0 stretch setting.
Note 2: Default stretch setting for external MOVX operations following reset, but reset before execution of ROM startup code.
Internal MOVX SRAM
The DS80C400 contains 9kB of SRAM that is physically divided into a 1kB block and an 8kB block. The 1kB block
can be used to support the extended stack-pointer function or can be used as general-purpose MOVX data
memory. The 8kB block is used by the Ethernet MAC as frame-buffer memory for incoming or outgoing packet data
and can, at the same time, be accessed by the DS80C400 as MOVX data memory. While the MAC is in use,
special care should be taken by user software to prevent undesirable MOVX writes from corrupting frame-buffer
memory. The address mapping of the 1kB block and the 8kB block are governed by the internal data-memory
configuration bits (IDM1, IDM0) in the memory control register (MCON;C6h). Note that when the SA bit (ACON.2)
is set, 1kB of the MOVX data memory is accessed by the 10-bit expanded stack pointer. Changing the IDM1:0
configuration bits while SA = 1 does not disrupt the extended stack-pointer function. Internal MOVX memory
accesses do not generate WR or RD strobes.
The DS80C400 contains an additional 256 Bytes of internal SRAM that is used to configure and operate the 15
CAN-controller message centers. The address location of this 256-Byte block is determined by the CAN data-
memory assignment bit (CMA) in the memory control register (MCON; C6h).
Table 10. Internal MOVX SRAM Configuration
Extended Stack Pointer
The DS80C400 supports both the traditional 8-bit and an extended 10-bit stack pointer that improves the
performance of large programs written in high-level languages such as C. To enable the 10-bit stack pointer, set
the stack-address mode bit, SA (ACON.2). The bit is cleared following a reset, forcing the device to use an 8-bit
stack located in the scratchpad RAM area. When the SA bit is set, the device addresses up to 1kB of internal
MOVX memory for stack purposes. The 10-bit stack pointer address is generated by concatenating the lower two
bits of the extended stack pointer (ESP;9Bh) and the traditional 8051 stack pointer (SP;81h).
On-Chip Arithmetic Accelerator
An on-chip math accelerator allows the microcontroller to perform 32-bit and 16-bit multiplication, division, shifting,
and normalization using dedicated hardware. Math operations are performed by sequentially loading three special
registers. The mathematical operation is determined by the sequence in which three dedicated SFRs (MA, MB, and
MCNT0) are accessed, eliminating the need for a special step to choose the operation. The normalize function
IDM1
MD2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
MD1
IDM0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
MD0
0
1
0
1
0
1
0
1
CMA
0
1
0
1
0
1
STRETCH
0 (Note 1)
1 (Note 2)
VALUE
2
3
4
5
6
7
(MAC/MOVX DATA)
FFE000h–FFFFFFh
FFE000h–FFFFFFh
00E000h–00FFFFh
00E000h–00FFFFh
000000h–001FFFh
000000h–001FFFh
8kB BLOCK
MACHINE
CYCLES
MOVX
10
11
12
2
3
4
5
9
47 of 97
CD1:0 = 00)
(4X/2X = 1
0.5 t
1 t
2 t
3 t
4 t
5 t
6 t
7 t
(STACK/MOVX DATA)
CLK
CLK
CLK
CLK
CLK
CLK
CLK
FFDC00h–FFDFFFh
FFDC00h–FFDFFFh
00DC00h–00DFFFh
00DC00h–00DFFFh
CLK
002000h–0023FFh
002000h–0023FFh
1kB BLOCK
APPROXIMATE RD, WR PULSE WIDTH
CD1:0 = 00)
(IN OSCILLATOR CLOCKS)
(4X/2X = 0
10 t
12 t
14 t
1 t
2 t
4 t
6 t
8 t
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CD1:0 = 10)
(4X/2X = X
12 t
16 t
20 t
24 t
28 t
2 t
4 t
8 t
(CAN DATA MEMORY)
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
FFDB00h–FFDBFFh
FFDB00h–FFDBFFh
FFDB00h–FFDBFFh
00DB00h–00DBFFh
00DB00h–00DBFFh
00DB00h–00DBFFh
256-BYTE
CD1:0 = 11)
(4X/2X = X
1024 t
2048 t
3072 t
4096 t
5120 t
6144 t
7168 t
512 t
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK

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