DS80C411 Maxim, DS80C411 Datasheet - Page 3

• Manufacturer Part Number: DS80C411
• Description: The DS80C410/DS80C411 network microcontrollers offer the highest integration available in an 8051 device
• Manufacturer: Maxim

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Note 13:
Specifications to -40°C are guaranteed by design and not production tested.
The user should note that this part is tested and guaranteed to operate down to V
thresholds for those supplies, V
given supply is greater than the guaranteed minimum operating voltage, that reset threshold should be considered the minimum
operating point since execution ceases once the part enters the reset state. When the reset threshold for a given supply is lower
than the guaranteed minimum operating voltage, there exists a range of voltages for either supply, (V
< V
be an issue in most applications, but should be considered when proper operation must be maintained at all times. For these
applications, it may be desirable to use a more accurate external reset.
While the specifications for V
ranges given, there is a guaranteed separation between these two voltages.
Current measured with 75MHz clock source on XTAL1, V
disconnected.
While the specifications for V
ranges given, there will be a guaranteed separation between these two voltages.
Certain pins exhibit stronger drive capability when being used to address external memory. These pins and associated memory
interface function (in parentheses) are as follows: Port 3.6-3.7 (WR, RD), Port 4 (CE0-3, A16-A19), Port 5.4-5.7 (PCE0-3), Port 6.0-
6.5 (CE4-7, A20, A21), Port 7 (demultiplexed mode A0-A7).
This measurement reflects the weak I/O pullup state that persists following the momentary strong 0 to 1 port pin drive (V
I/O pin state can be achieved by applying RST = V
The measurement reflects the momentary strong port pin drive during a 0-to-1 transition in I/O mode. During this period, a one shot
circuit drives the ports hard for two clock cycles. A weak pullup device (V
drive. If a port 4 or 6 pin is functioning in memory mode with pin state of 0 and the SFR bit contains a 1, changing the pin to an I/O
mode (by writing to P4CNT, for example) does not enable the two-cycle strong pullup.
Port 3 pins 3.6 (WR) and 3.7(RD) have a stronger than normal pullup drive for only one system clock period following the transition
of either WR or RD from a 0 to a 1.
This is the current required from an external circuit to hold a logic low level on an I/O pin while the corresponding port latch bit is set
to 1. This is only the current required to hold the low level; transitions from 1 to 0 on an I/O pin also have to overcome the transition
current.
Following the 0 to 1 one-shot timeout, ports in I/O mode source transition current when being pulled down externally. It reaches a
maximum at approximately 2V.
During external addressing mode, weak latches are used to maintain the previously driven state on the pin until such time that the
Port 0 pin is driven by an external memory source.
The OW pin (when configured to output a 1) at V
CRS, COL, MDIO) at V
CC1
< 3.0V), where the processor’s operation is not guaranteed, and the reset trip point has not been reached. This should not
IN
= 3.6V.
PFW3
PFW1
RST3
and V
and V
and V
RST3
RST1
RST1
overlap, the design of the hardware makes it such that this is not possible. Within the
overlap, the design of the hardware makes it such that this is not possible. Within the
respectively, may be above or below those points. When the reset threshold for a
IN
CC3.
= 5.5V, EA, MUX, and all MII inputs (TXCLk, RXCLk, RX_DV, RX_ER, RXD[3:0],
3 of 102
CC3
= 3.6V, V
CC1
OH1
= 2.0V, EA and RST = 0V, Port0 = V
) remains in effect following the strong two-clock cycle
CC3
= 3.0V and V
CC1
RST3
= 1.62V, while the reset
< V
CC3
CC3
< 1.62V) or (V
, all other pins
OH2
). This
RST1