71M6531D Maxim, 71M6531D Datasheet - Page 62
71M6531D
Manufacturer Part Number
71M6531D
Description
The 71M6531D/F and 71M6532D/F are highly integrated SoC devices with an MPU core, RTC, flash, and LCD driver
Manufacturer
Maxim
Datasheet
1.71M6531D.pdf
(120 pages)
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MPU via shared registers in the I/O RAM and in RAM.
The CE outputs two interrupt signals to the MPU: CE_BUSY and XFER_BUSY, which are connected to
the MPU interrupt service inputs as external interrupts. CE_BUSY indicates that the CE is actively
processing data. This signal will occur once every multiplexer cycle. XFER_BUSY indicates that the CE
is updating data to the output region of the RAM. This will occur whenever the CE has finished generating
a sum by completing an accumulation interval determined by SUM_CYCLES[5:0] * PRE_SAMPS[1:0] samples.
Interrupts to the MPU occur on the falling edges of the XFER_BUSY and CE_BUSY signals.
Refer to Section
MPU firmware.
Data Sheet 71M6531D/F-71M6532D/F
2.7
Figure 27
62
Mux Control
ADC
CE/MPU Communication
shows the functional relationships between the CE and the MPU. The CE is controlled by the
4.3 CE Interface Description
Samples
SAMPLES
(DIO7)
I/O RAM (Configuration RAM)
VAR
© 2005-2010 TERIDIAN Semiconductor Corporation
CE
Figure 27: MPU/CE Communication
Pulses
Processor
I/O RAM (Configuration RAM)
CE
W (DIO6)
Pre -
PULSES
Figure 26: MPU/CE Data Flow
for additional information on setting up the device using the
SAG CONTROL
IRQ
Data
INTERRUPTS
XFER BUSY
EXT PULSE
APULSEW
APULSER
CE BUSY
DATA
Processor
MPU
Post -
MPU
Processed
Metering
Data
FDS 6531/6532 005
DISPLAY (Memory
mapped LCD
segments)
SERIAL
(UART0/1)
EEPROM
(I
DIO
2
C)
v1.3
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