MC10E1651L ON Semiconductor, MC10E1651L Datasheet

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MC10E1651L

Manufacturer Part Number
MC10E1651L
Description
IC COMPARATOR DUAL ECL 16-CDIP
Manufacturer
ON Semiconductor
Series
MOSAIC III™r
Type
with Latchr
Datasheet

Specifications of MC10E1651L

Number Of Elements
2
Output Type
Differential, ECL
Mounting Type
Through Hole
Package / Case
16-CDIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC10E1651L
Manufacturer:
HITACHI
Quantity:
200
MC10E1651
5V, -5V Dual ECL Output
Comparator with Latch
advanced MOSAIC III™ process. The MC10E1651 incorporates a
fixed level of input hysteresis as well as output compatibility with 10
KH logic devices. In addition, a latch is available allowing a sample
and hold function to be performed. The device is available in both a
16‐pin DIP and a 20‐pin surface mount package.
ECL 10 KH logic levels. When the latch enable is at a logic high level,
the MC10E1651 acts as a comparator; hence, Q will be at a logic high
level if V1 > V2 (V1 is more positive than V2). Q is the complement
of Q. When the latch enable input goes to a low logic level, the outputs
are latched in their present state providing the latch enable setup and
hold time constraints are met.
Features
*For additional information on our Pb-Free strategy and soldering details, please
© Semiconductor Components Industries, LLC, 2007
August, 2007 - Rev. 9
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
The MC10E1651 is fabricated using ON Semiconductor's
The latch enable (LEN
> 100 V Machine Model
For Additional Information, see Application Note AND8003/D
Oxygen Index: 28 to 34
Typical 3.0 dB Bandwidth > 1.0 GHz
Typical V to Q Propagation Delay of 775 ps
Typical Output Rise/Fall of 350 ps
Common Mode Range -2.0 V to +3.0 V
Individual Latch Enables
Differential Outputs
28 mV Input Hysteresis
Operating Mode: V
No Internal Input Pulldown Resistors
ESD Protection: > 2 kV Human Body Model,
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Moisture Sensitivity Level 1
Flammability Rating: UL 94 V-0 @ 0.125 in,
Transistor Count = 85 devices
Pb-Free Packages are Available*
CC
a
= 5.0 V, V
and LEN
b
EE
) input pins operate from standard
= -5.2 V, GND = 0 V
1
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
20 1
CASE 620A
FN SUFFIX
CASE 775
L SUFFIX
PLCC-20
CDIP-16
ORDERING INFORMATION
A
WL
YY
WW
G
http://onsemi.com
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb-Free Package
Publication Order Number:
16
1
DIAGRAMS
MC10E1651L
AWLYYWW
MARKING
AWLYYWW
MC10E1651/D
1651FNG
MC10E
1 20

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MC10E1651L Summary of contents

Page 1

... Semiconductor Components Industries, LLC, 2007 August, 2007 - Rev -5.2 V, GND = 0 V See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet. 1 http://onsemi.com MARKING DIAGRAMS 16 MC10E1651L AWLYYWW 1 CDIP-16 L SUFFIX CASE 620A 1 20 MC10E 1651FNG 20 1 AWLYYWW ...

Page 2

Qb LEN NC V1b V2b GND 20 20‐Lead PLCC (Top View GND LEN NC V2a V1a a * All V Warning: All V ...

Page 3

Table 3. MAXIMUM RATINGS Symbol Parameter V Total Supply Voltage SUP V Differential Input Voltage PP V Input Voltage I I Output Current out T Operating Temperature Range A T Storage Temperature Range stg q Thermal Resistance (Junction-to-Ambient ...

Page 4

Table 5. AC CHARACTERISTICS V Symbol Characteristic f Maximum Toggle Frequency MAX t Propagation Delay to Output (Note 4) PLH t PHL t Setup Time Enable Hold Time Minimum Pulse Width LEN pw t ...

Page 5

The timing diagram (Figure 3.) is presented to illustrate the MC10E1651's compare and latch features. When the signal on the LEN pin logic high level, the device is operating in the “compare mode,” and the signal on ...

Page 6

Under a constant set of input conditions comparators have a specified nominal propagation delay. However, since propagation delay is a function of input slew rate and input voltage overdrive the delay dispersion parameters are provided to allow ...

Page 7

... Q Figure 6. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D - Termination of ECL Logic Devices.) ORDERING INFORMATION Device MC10E1651L MC10E1651FN MC10E1651FNG MC10E1651FNR2 MC10E1651FNR2G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D ...

Page 8

0.25 (0.010) MC10E1651 PACKAGE DIMENSIONS CDIP-16 L SUFFIX CERAMIC DIP PACKAGE CASE 620A-01 ISSUE 16X 0.25 (0.010 SEATING T ...

Page 9

Y BRK -L- - 0.007 (0.180) Z 0.007 (0.180 -T- J VIEW S G1 0.010 (0.250 NOTES: 1. DIMENSIONS AND TOLERANCING PER ANSI Y14.5M, ...

Page 10

... Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT:  Literature Distribution Center for ON Semiconductor  P.O. Box 5163, Denver, Colorado 80217 USA  Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada  Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada   ...

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