STHDLS101TQTR STMicroelectronics, STHDLS101TQTR Datasheet

IC HDMI LEVEL SHIFTER AC 48-QFN

STHDLS101TQTR

Manufacturer Part Number
STHDLS101TQTR
Description
IC HDMI LEVEL SHIFTER AC 48-QFN
Manufacturer
STMicroelectronics
Type
Level Shifterr
Datasheet

Specifications of STHDLS101TQTR

Function
*
Circuit
*
On-state Resistance
*
Voltage Supply Source
*
Voltage - Supply, Single/dual (±)
*
Current - Supply
*
Operating Temperature
*
Mounting Type
Surface Mount
Package / Case
48-QFN
Applications
Graphic Cards, VGA Interfaces
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-8499-2

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Features
Applications
Table 1.
December 2008
Converts low-swing alternating current (AC)
coupled differential input to high-definition
multimedia interface (HDMI) rev 1.3 compliant
HDMI level shifting operation up to 2.7 Gbps
per lane
Integrated 50-Ω termination resistors for AC-
coupled differential inputs
Input/output transition minimized differential
signaling (TMDS) enable/disable
Output slew rate control on TMDS outputs to
minimize electromagnetic interference (EMI)
Fail safe outputs for backdrive protection
No re-timing or configuration required
Inter-pair output skew < 250 ps
Intra-pair output skew < 10 ps
Single power supply of 3.3 V
ESD protection: ±6 KV HBM on all I/O pins
Integrated display data channel (DDC) level
shifters. Pass-gate voltage limiters allow 3.3 V
termination on graphics and memory controller
hub (GMCH) pins and 5 V DDC termination on
HDMI connector pins
Level shifter and configurable output for HPD
signal from HDMI/DVI connector
Integrated pull-down resistor on HPD_SINK
and OE_N inputs
Notebooks
PC motherboards and graphic cards
Dongles/cable adapters
STHDLS101TQTR
Order code
Device summary
Package
QFN-48
Rev 3
Description
The STHDLS101T is a high-speed high-definition
multimedia interface (HDMI) level shifter that
converts low-swing AC coupled differential input
to HDMI 1.3 compliant open-drain current
steering RX-terminated differential output.
Through the existing PCI-E pins in the graphics
and memory controller hub (GMCH) of PCs or
notebook motherboards, the pixel clock provides
the required bandwidth (1.65 Gbps, 2.25 Gbps)
for the video supporting 720p, 1080i, 1080p with a
total of 36-bit resolution. The HDMI is multiplexed
onto the PCIe pins in the motherboard where the
AC coupled HDMI at 1.2 V is output by GMCH.
The AC coupled HDMI is then level shifter by this
device to 3.3 V DC coupled HDMI output.
The STHDLS101T supports up to 2.7 Gbps,
which is enough for 12-bits of color depth per
channel, as indicated in HDMI rev 1.3. The device
operates from a single 3.3 V supply and is
available in a 48-pin QFN package.
AC coupled HDMI level shifter
with configurable HPD output
(7 x 7 mm)
STHDLS101T
QFN-48
Tape and reel
Packaging
www.st.com
1/26
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STHDLS101TQTR Summary of contents

Page 1

... Applications ■ Notebooks ■ PC motherboards and graphic cards ■ Dongles/cable adapters Table 1. Device summary Order code STHDLS101TQTR December 2008 STHDLS101T AC coupled HDMI level shifter with configurable HPD output QFN- mm) Description The STHDLS101T is a high-speed high-definition multimedia interface (HDMI) level shifter that converts low-swing AC coupled differential input to HDMI 1 ...

Page 2

Contents Contents 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 3

STHDLS101T Contents 3/26 ...

Page 4

Block diagram 1 Block diagram Figure 1. STHDLS101T block diagram VCC33 50 ±10% IN _D4+ IN _D4- OE_N 50 ±10% IN _D3+ IN _D3- 50 ±10% IN _D2+ IN _D2 _D1+ IN _D1- REXT HPD_SOURCE DDC_EN SCL_SOURCE SDA_SOURCE ...

Page 5

STHDLS101T 2 System interface Figure 2. System inferface Graphics chipset (GMCH) on the motherboard Figure 3. Cable adapter PCI-Express SDVO HDMI Level shifter STHDLS101T System interface HDMI output connector CS00375 5/26 ...

Page 6

System interface Figure HDMI/DVI cable adapter HDMI/DVI Transmitter PC chipset 6/26 HPD HPD_SOURCE STHDLS101T AC_TMDS AC_TMDS HDMI/DVI Cable Adaptor DDC DDC STHDLS101T HPD_SINK DC TMDS DDC ...

Page 7

STHDLS101T 3 Pin configuration Figure 5. STHDLS101T pin configuration IN_D1+ VCC33 GND 37 IN_D1 IN_D2- 41 QFN-48 IN_D2+ 42 GND 43 IN_D3- 44 IN_D3+ 45 VCC33 46 IN_D4- 47 IN_D4+ 48 Pin configuration GND 24 OUT_D1- 23 ...

Page 8

Pin configuration 3.1 Pin description Table 2. Pin description Pin Name number 1 GND 2 VCC33 3 FUNCTION1 4 FUNCTION2 5 GND 6 REXT 7 HPD_SOURCE 8 SDA_SOURCE 9 SCL_SOURCE 8/26 Type Power Ground Power 3.3V±10% DC supply Function pins ...

Page 9

STHDLS101T Table 2. Pin description (continued) Pin Name number 10 ANALOG2 11 VCC33 12 GND 13 OUT_D4+ 14 OUT_D4- 15 VCC33 16 OUT_D3+ 17 OUT_D3- 18 GND 19 OUT_D2+ 20 OUT_D2- 21 VCC33 22 OUT_D1+ 23 OUT_D1- 24 GND 25 ...

Page 10

Pin configuration Table 2. Pin description (continued) Pin Name number 27 GND 28 SCL_SINK 29 SDA_SINK 30 HPD_SINK 31 GND 32 DDC_EN 33 VCC33 34 FUNCTION3 35 FUNCTION4 36 GND 37 GND 38 IN_D1- 39 IN_D1+ 40 VCC33 41 IN_D2- ...

Page 11

STHDLS101T Table 2. Pin description (continued) Pin Name number 43 GND 44 IN_D3- 45 IN_D3+ 46 VCC33 47 IN_D4- 48 IN_D4+ Type Power Ground Low-swing differential input from GMCH PCIE outputs. Input IN_D3- makes a differential pair with IN_D3+. Low-swing ...

Page 12

Functional description 4 Functional description The section describes the basic functionality of the STHDLS101T device. Power supply The STHDLS101T is powered by a single DC power supply of 3.3 V ± 10%. Clocking This device does not retime any data. ...

Page 13

STHDLS101T Table 4. OE_N function OE_N De-asserted (high level) Asserted or unconnected (low level) OUT_Dx IN_Dx (TMDS outputs) High-Z High-Z 50 Ω termination Enabled Functional description Notes Device disabled. Low power state. Internal bias currents are disabled. Level shifting mode ...

Page 14

... These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 5. ...

Page 15

STHDLS101T 5.1 Recommended operating conditions 5.1.1 Power supply and temperature range Table 7. Power supply and temperature range Symbol Parameter V 3.3 V power supply CC33 I Maximum power supply current CC T Operating temperature range 5.1.2 Differential inputs (IN_D ...

Page 16

Maximum ratings 5.2 TMDS outputs (OUT_D signals) The level shifter’s TMDS outputs are required to meet the HDMI 1.3 specifications. The HDMI 1.3 specification is assumed to be the correct reference in instances where this document conflicts with the HDMI ...

Page 17

STHDLS101T 5.3 HPD input and output characteristics Table 10. HPD_SINK input and HPS_SOURCE output Symbol Parameter V HPD_SINK input high level IH-HPD_SINK V HPD_SINK input low level IL-HPD_SINK I HPD_SINK input leakage current IN-HPD_SINK V OH- HPD_SOURCE output high level ...

Page 18

Maximum ratings 5.4 DDC input and output chatacteristics Table 11. SDA_SOURCE, SCL_SOURCE and SDA_SINK, SCL_SINK characteristics Symb Parameter ol V Input voltage on SDA_SINK, SCL_SINK pins I Input leakage current on SDA_SINK, SCL_SINK I LKG pins Power-down leakage current on ...

Page 19

STHDLS101T 5.5 OE_ input characteristics Table 12. OE_N input characteristics Symbol Parameter V Input high level IH-OE_N V Input low level IL-OE_N I Input leakage current IN-OE_N 5.6 HPD input resistor Table 13. HDP input resistor Symbol Parameter R HPD_SINK ...

Page 20

Application information 6 Application information 6.1 Power supply sequencing Proper power-supply sequencing is advised for all CMOS devices recommended to always apply V or control pins. 6.2 Supply bypassing Bypass each of the V device as possible, with ...

Page 21

STHDLS101T 7 Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the ...

Page 22

Package mechanical data Figure 6. QFN- mm) package outline 22/26 STHDLS101T ...

Page 23

STHDLS101T Table 15. QFN- mm) package mechanical data Symbol ddd Figure 7. QFN-48 tape and reel information Min Typ Max 0.80 0.90 1.00 0.02 0.05 0.65 ...

Page 24

Package mechanical data Figure 8. Reel information Table 16. Reel mechanical data (dimensions in mm) A 330.2 24/ ± 13 0.25 100 STHDLS101T 0084694_J T 16.4 ...

Page 25

STHDLS101T 8 Revision history Table 17. Document revision history Date 30-Jun-2008 24-Sep-2008 01-Dec-2008 Revision 1 Initial release. Document status promoted from preliminary data to datasheet. 2 Modified: features section, Section 4: Functional Updated: Features section Added: Figure 3: Cable adapter ...

Page 26

... Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...

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