EL4581CSZ-T7 Intersil, EL4581CSZ-T7 Datasheet

IC VIDEO SYNC SEPARATOR 8-SOIC

EL4581CSZ-T7

Manufacturer Part Number
EL4581CSZ-T7
Description
IC VIDEO SYNC SEPARATOR 8-SOIC
Manufacturer
Intersil
Type
Synchronous Separatorr
Datasheet

Specifications of EL4581CSZ-T7

Applications
Displays, Test Equipment, Video
Mounting Type
Surface Mount
Package / Case
8-SOIC (3.9mm Width)
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
EL4581CSZ-T7
EL4581CSZ-T7TR

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Manufacturer
Quantity
Price
Part Number:
EL4581CSZ-T7
Manufacturer:
Intersil
Quantity:
4 000
Part Number:
EL4581CSZ-T7
Manufacturer:
INTERSIL
Quantity:
11 884
Part Number:
EL4581CSZ-T7
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INTERSIL
Quantity:
9 895
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Part Number:
EL4581CSZ-T7
Quantity:
695
Sync Separator, 50% Slice, S-H, Filter
and SECAM broadcast systems. It can also be used in non
standard formats and with computer graphics systems at
higher scan rates, by adjusting a single external resistor.
When the input does not have correct serration pulses in the
vertical interval, a default vertical output is produced.
Outputs are composite sync, vertical sync, burst/back porch
output, and odd/even output. The later operates only in
interlaced scan formats.
The EL4581 provides a reliable method of determining
correct sync slide level by setting it to the mid-point between
sync tip and blanking level at the back porch. This 50% level
is determined by two internal self timing sample and hold
circuits that track sync tip and back porch levels. This also
provides a degree of hum and noise rejection to the input
signal, and compensates for varying input levels of 0.5V
to 2.0V
A built in linear phase, third order, low pass filter attenuates
the chroma signal in color systems to prevent incorrectly set
color burst from disturbing the 50% sync slide.
This device may be used to replace the industry standard
LM1881, offering improved performance and reduced power
consumption.
The EL4581 video sync separator is manufactured using
Elantec’s high performance analog CMOS process.
Pinout
P-P
COMPOSITE
COMPOSITE
.
SYNC OUT
SYNC OUT
VERTICAL
VIDEO IN
GND
The EL4581 extracts timing
information from standard negative
going video sync found in NTSC, PAL
(8 LD SOIC, PDIP)
1
2
3
4
TOP VIEW
EL4581
®
1
Data Sheet
Copyright © Intersil Americas Inc. 2003, 2008, 2010. All Rights Reserved. Elantec is a registered trademark of Elantec Semiconductor, Inc.
8
7
6
5
VDD 5V
ODD/EVEN OUTPUT
RSET
BURST/BACK
PORCH OUTPUT
1-888-INTERSIL or 1-888-468-3774
All other trademarks mentioned are the property of their respective owners. Manufactured under U.S. Patent 5,528,303.
P-P
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
|
Features
• NTSC, PAL and SECAM sync separation
• Single supply, +5V
• Precision 50% slicing, internal caps
• Built-in color burst filter
• Decodes non-standard verticals
• Pin compatible with LM1881
• Low power
• Typically 1.5mA supply current
• Resistor programmable scan rate
• Few external components
• Available in 8 Ld PDIP and SOIC packages
• Pb-free available (RoHS compliant)
Applications
• Video special effects
• Video test equipment
• Video distribution
• Displays
• Imaging
• Video data capture
• Video triggers
Ordering Information
Demo Board
A dedicated demo board is not available. However, this
device can be placed on the EL4584/5 Demo Board.
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
EL4581CN
EL4581CS*
EL4581CSZ*
(Note)
*Add “-T7” or “-T13” suffix for tape and reel. Please refer to TB347 for
details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special
Pb-free material sets; molding compounds/die attach materials and 100%
matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS
compliant and compatible with both SnPb and Pb-free soldering
operations. Intersil Pb-free products are MSL classified at Pb-free peak
reflow temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
November 12, 2010
NUMBER
PART
EL4581CN
4581CS
4581CSZ
MARKING
PART
TEMP. RANGE
-40°C to +85°C 8 Ld PDIP
-40°C to +85°C 8 Ld SOIC
-40°C to +85°C 8 Ld SOIC
(Pb-free)
PACKAGE
EL4581
FN7172.2
MDP0031
MDP0027
MDP0027
DWG. #
PKG.

Related parts for EL4581CSZ-T7

EL4581CSZ-T7 Summary of contents

Page 1

... Video data capture • Video triggers Ordering Information PART NUMBER EL4581CN EL4581CS* VDD 5V EL4581CSZ* ODD/EVEN OUTPUT (Note) RSET *Add “-T7” or “-T13” suffix for tape and reel. Please refer to TB347 for details on reel specifications. BURST/BACK PORCH OUTPUT NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets ...

Page 2

... Parts are 100% tested at +25°C. Over-temperature limits established by characterization and are not production tested. 2 EL4581 Thermal Information = +25°C) Maximum Power Dissipation See Curves Maximum Junction Temperature +150°C +0.5V Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below CC http://www.intersil.com/pbfree/Pb-FreeReflow.asp = 5V +25° DESCRIPTION TEMP (° ...

Page 3

Pin Descriptions PIN NUMBER PIN NAME 1 Composite Sync Out 2 Composite Video in 3 Vertical Sync Out 4 GND 5 Burst/Back Porch Output 6 RSET (Note 8) 7 Odd/Even Output 8 VDD 5V NOTE must be a ...

Page 4

Typical Performance Curves PACKAGE POWER DISSIPATION VS AMBIENT TEMPERATURE JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 2.0 1.8 1.6 1.471W PDIP8 1.4 θ = 85°C/W JA 1.2 1.0 1.136W 0.8 0.6 SO8 0.4 θ = 110°C/W JA 0.2 0 ...

Page 5

Timing Diagrams SIGNAL 1a. COMPOSITE VIDEO INPUT, FIELD ONE 1.5µs±230µs TIME VERTICAL BLANKING INTERVAL = 20H SYNC START OF INTERVAL FIELD ONE PRE-EQUALIZING H PULSE INTERVAL SIGNAL 1b. COMPOSITE SYNC OUTPUT, PIN 1 SIGNAL 1c. VERTICAL ...

Page 6

Timing Diagrams (Continued) SIGNAL 2a. COMPOSITE VIDEO INPUT SIGNAL 2b. COMPOSITE SYNC OUTPUT SIGNAL 2c. VERTICAL SYNC OUTPUT SIGNAL 2d. ODD-EVEN OUTPUT SIGNAL 2e. BURST/BACK PORCH OUTPUT SIGNAL 3a. COMPOSITE VIDEO INPUT SIGNAL 3b. VERTICAL SYNC OUTPUT 6 EL4581 SLICE ...

Page 7

INPUT DYNAMIC RANGE 0. 50% t COMPOSITE SYNC OUTPUT, PIN 1 BACK PORCH OUTPUT, PIN 5 Description of Operation A simplified block diagram is shown in Figure 13. The following description is intended to provide the user with ...

Page 8

V initiates the timing one-shots for gating the sample and hold circuits. The sample of the sync tip is delayed by 0.8µs to enable the actual sample of 2µ taken on the ...

Page 9

Small Outline Package Family (SO PIN #1 I.D. MARK 0.010 SEATING PLANE 0.004 C 0.010 MDP0027 SMALL OUTLINE PACKAGE FAMILY (SO) SYMBOL SO-8 SO-14 ...

Page 10

... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...

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