ISL98001CQZ-170 Intersil, ISL98001CQZ-170 Datasheet
ISL98001CQZ-170
Specifications of ISL98001CQZ-170
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ISL98001CQZ-170 Summary of contents
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... All other trademarks mentioned are the property of their respective owners. ISL98001 FN6148.5 @ 170MSPS) P-P to 1.4V video input range P-P ABLC™ RGB/YUV OUT x3 HSYNC OUT VSYNC OUT HS OUT PIXELCLK OUT | Intersil (and design registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005-2007, 2010. All Rights Reserved ...
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... PART NUMBER (Note) ISL98001IQZ-140 ISL98001CQZ-140 ISL98001CQZ-170 ISL98001CQZ-210 ISL98001CQZ-275 NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020 ...
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... Thermal Information Thermal Resistance, Typical (Note 1) MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . Maximum Biased Junction Temperature . . . . . . . . . . . . . . . . +125°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C A Pb-Free Reflow Profile .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions Temperature Commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C Industrial .-40°C to +85°C Supply Voltage ...
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Electrical Specifications Specifications apply for V ISL98001-170, 210MHz for ISL98001-210, or 275MHz for ISL98001-275, f otherwise noted. (Continued) SYMBOL PARAMETER ANALOG VIDEO INPUT CHARACTERISTICS (R Input Range Input Bias Current Input Capacitance Full Power Bandwidth INPUT CHARACTERISTICS (SOG 1, SOG ...
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Electrical Specifications Specifications apply for V ISL98001-170, 210MHz for ISL98001-210, or 275MHz for ISL98001-275, f otherwise noted. (Continued) SYMBOL PARAMETER I Digital Supply Current D I Crystal Oscillator Supply Current X P Total Power Dissipation D ISL98001-140 ISL98001-170 ISL98001-210 ISL98001-275 ...
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F SCL t t SU:STA t HD:STA SDA IN SDA OUT DATACLK DATACLK Pixel Data FIGURE 2. DATA OUTPUT SETUP AND HOLD TIMING HSYNC IN Analog Video In DATACLK [7: ...
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The HSYNC edge (programmable leading or trailing) that the DPLL is locked to. HSYNC IN The sampling phase setting determines its relative position to the rest of the AFE’s output signals Analog Video In DATACLK G [7:0] ...
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HSYNC IN Analog P 0 Video In DATACLK [7: [7: OUT FIGURE 6. 48-BIT OUTPUT MODE, INTERLEAVED TIMING 8 ISL98001 The HSYNC edge (programmable leading or trailing) ...
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Pin Configuration (MQFP, ISL98001 GND BYPASS GND GND BYPASS GND ...
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Pin Descriptions SYMBOL MQFP PIN #( Analog input. Red Channel 1. DC couple or AC couple through 0.1µ Analog input. Green Channel 1. DC couple or AC couple through 0.1µ ...
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Pin Descriptions (Continued) SYMBOL MQFP PIN #(s) VS 126 3.3V digital output. Artificial VSYNC output aligned with pixel data. VS OUT the trailing edge of HS HSYNC 127 3.3V digital output. Buffered HSYNC (or SOG or CSYNC) output. This is ...
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Register Listing ADDRESS REGISTER (DEFAULT VALUE) 0x00 Device ID (read only) 0x01 SYNC Status (read only) 0x02 SYNC Polarity (read only) 0x03 HSYNC Slicer (0x33) 0x04 SOG Slicer (0x16) Note: Due to normal device-to-device variation in slicer levels, SOG Slicer ...
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Register Listing (Continued) ADDRESS REGISTER (DEFAULT VALUE) 0x05 Input configuration (0x00) 0x06 Red Gain (0x55) 0x07 Green Gain (0x55) 0x08 Blue Gain (0x55) 13 ISL98001 BIT(S) FUNCTION NAME 0 Channel Select 0: VGA1 1: VGA2 1 Input Coupling 0: AC ...
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Register Listing (Continued) ADDRESS REGISTER (DEFAULT VALUE) 0x09 Red Offset (0x80) 0x0A Green Offset (0x80) 0x0B Blue Offset (0x80) 0x0C Offset DAC Configuration (0x00) 0x0D AFE Bandwidth (0x2E) 0x0E PLL Htotal MSB (0x03) 0x0F PLL Htotal LSB (0x20) 0x10 PLL ...
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Register Listing (Continued) ADDRESS REGISTER (DEFAULT VALUE) 0x13 PLL Misc (0x04) 0x14 DC Restore and ABLC starting pixel MSB (0x00) 0x15 DC Restore and ABLC starting pixel LSB (0x03) 0x16 DC Restore Clamp Width (0x10) 0x17 ABLC Configuration (0x40) 15 ...
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Register Listing (Continued) ADDRESS REGISTER (DEFAULT VALUE) 0x18 Output Format (0x00) 0x19 HS Width (0x10) OUT 0x1A Output Signal Disable (0x00) 0x1B Power Control (0x00) 0x1C PLL Tuning (0x49) 16 ISL98001 BIT(S) FUNCTION NAME 0 Bus Width 0: 24-bits: Data ...
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Register Listing (Continued) ADDRESS REGISTER (DEFAULT VALUE) 0x1D Red ABLC Target (0x00) 0x1E Green ABLC Target (0x00) 0x1F Blue ABLC Target (0x00) 0x23 DC Restore Clamp (0x18) 17 ISL98001 BIT(S) FUNCTION NAME 7:0 Red ABLC Target This is a 2's ...
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Register Listing (Continued) ADDRESS REGISTER (DEFAULT VALUE) 0x25 Sync Separator Control (0x00) 0x2B Crystal Multiplier (0x14) Technical Highlights The ISL98001 provides all the features of traditional triple channel video AFEs, but adds several next-generation enhancements, bringing performance and ease of ...
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Automatic Black Level Compensation (ABLC™) and Gain Control Traditional video AFEs have an offset DAC prior to the ADC, to both correct for offsets on the incoming video signals and add/subtract an offset for user “brightness control” without sacrificing the ...
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DC Restoration GENERATION V CLAMP DC Restore Clamp DAC R(GB VGA1 IN R(GB) 1 GND PGA R(GB VGA2 R(GB) 2 GND The ISL98001 can optionally decimate the incoming data to provide ...
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... If the OUT Intersil’s DPLL has the capability to correct large phase changes almost instantly by maximizing the phase error gain while keeping the frequency gain relatively low. This is done by changing the contents of register 0x1C to 0x4C. This increases the phase error gain to 100% ...
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PGA The ISL98001’s Programmable Gain Amplifier (PGA) has a nominal gain range from 0.5V/V (-6dB) to 2.0V/V (+6dB). The transfer function is in Equation 1: V GainCode ⎛ ⎞ --- - Gain = 0.5 + ---------------------------- - ⎝ ⎠ V ...
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TABLE 6. OFFSET DAC RANGE AND OFFSET DAC ADJUSTMENT OFFSET 10-BIT DAC RANGE OFFSET DAC ABLC 0X0C[0] RESOLUTION 0x17[0] 0 0.25 ADC LSBs (0.68mV) (ABLC on) 1 0.125 ADC LSBs (0.34mV) (ABLC on) 0 0.25 ADC LSBs (0.68mV) (ABLC off) ...
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HSYNC VSYNC SOG DETECT DETECT DETECT SOG Slicer The SOG input has programmable threshold, 40mV of hysteresis, and an optional low pass filter that can ...
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... HSYNC trailing edge). Its width, in units of lines, is equal to the width of the incoming VSYNC (See the VSYNC determined by register 0x18[6]. Note: This output is not needed in most applications. Intersil strongly discourages using this signal - use VSYNC (including the sync separator OUT is generated by the ISL98001’ ...
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Crystal Oscillator An external 22MHz to 27MHz crystal supplies the low-jitter reference clock to the DPLL. The absolute frequency of this crystal within this range is unimportant the crystal’s temperature coefficient, allowing use of less expensive, lower-grade crystals. ...
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... If the databus is heavily loaded (long traces, many other part on the same bus), this value may need to be reduced. If the databus is lightly loaded, it may be increased. Intersil’s recommendations to minimize EMI are: • Minimize the databus trace length • Minimize the databus capacitive loading. ...
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SCL SDA Start FIGURE 9. VALID START AND STOP CONDITIONS SCL from Host 1 Data Output from Transmitter Data Output from Receiver Start FIGURE 10. ACKNOWLEDGE RESPONSE FROM RECEIVER SCL SDA Data Stable FIGURE 11. VALID DATA CHANGES ON THE ...
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START Command ISL98001 Serial Bus (Repeat if desired) STOP Command S T Serial Bus Register A Signals from Address Address R the Host T 1 ...
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START Command ISL98001 Serial Bus START Command ISL98001 Serial Bus (Repeat if desired) STOP Command S T Serial Bus Register ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...