LMH0031VS/NOPB National Semiconductor, LMH0031VS/NOPB Datasheet - Page 18

• Manufacturer Part Number: LMH0031VS/NOPB
• Description: IC DESER/DESCRAM DGTL VID 64TQFP
• Manufacturer: National Semiconductor
• Type: Descrambler/Deserializerr

Specifications of LMH0031VS/NOPB

• Applications: SDTV/HDTV
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Input Voltage: 3.3 V
• Supply Voltage (max): 3.45 V
• Supply Voltage (min): 3.15 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• For Use With: SD131EVK - BOARD EVALUATION LMH0031
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *LMH0031VS; *LMH0031VS/NOPB; LMH0031VS

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FIFO-DEPTH(2)
EDH 0 (register address 01h)
EDH 1 (register address 02h)
EDH 2 (register address 03h)
ANC 0 (register address 04h)
ANC 1 (register address 05h)
ANC 2 (register address 06h)
ANC 3 (register address 07h)
ANC 4 (register address 08h)
ANC 5 (register address 17h)
LSB Clipping Enable
Sync Detect Enable
De-Dither Enable
Vert. De-Dither Enable
Lock Detect
Unscrambled
Video Data Out
TPG and BIST Operations
Test Pattern Select
TPG Enable
Pass/Fail
VPG Filter Enable
Reference Clock Operations
Reference Clock
External Vclk
Multifunction I/O Bus Operations
I/O Bus Pin Config.
ANC MASK(7)
CRC ERROR
Device Operation
ANC ID(15)
Note 11: Connected to multifunction I/O port at power-on.
Note 12: ON = SET = logic-1, OFF = RESET = logic-0 (positive logic).
Note 13: Special or restricted functionality. Refer to text for details.
REPLACE
ANC ID(7)
EXTRACT
MASK(15)
F/F FLAG
ENABLE
ERROR
VIDEO
Register Function
FIFO
Bit 7
CRC
ANC
FIFO-DEPTH(1)
ANC MASK(14) ANC MASK(13)
ANC MASK(6)
CRC ERROR
FIFO CLOCK
EDH FORCE
ANC ID(14)
ANC ID(6)
A/P FLAG
ENABLE
ERROR
VIDEO
LUMA
Bit 6
TABLE 1. Configuration and Control Data Register Summary (Continued)
(Continued)
Bits
48
FIFO-DEPTH(0)
1
1
1
1
1
1
6
1
1
1
2
1
ANC MASK(5)
EDH ENABLE
CRC ERROR
ANC ID(13)
AVAILABLE
ANC FLAG
FULL MSG
ANC ID(5)
CHROMA
ERROR
VIDEO
Bit 5
TABLE 2. Control Register Bit Assignments
Read or Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
ANC ID(12)
OVERRUN
ANC FIFO
ANC ID(4)
ANC UES
MASK(12)
A/P UES
MASK(4)
F/F UES
reserved
Bit 4
ANC
ANC
18
Initial Condition
See Table 6
FIFO FLUSH
ANC ID(11)
000000b
ANC FIFO
ANC ID(3)
MASK(11)
ANC IDA
MASK(3)
F/F IDA
A/P IDA
EMPTY
STATIC
OFF
OFF
OFF
OFF
OFF
OFF
00b
ON
ON
Bit 3
ANC
ANC
ANC ID(10)
ANC FIFO
ANC ID(2)
MASK(10)
ANC IDH
MASK(2)
reserved
A/P IDH
F/F IDH
FULL
Bit 2
ANC
ANC
Available on
I/O Bus
Output
Output
Input
Input
Input
Input
Input
No
No
No
No
No
No
ANC CHECK-
SUM ERROR
MSG FLUSH
ANC ID(1)
ANC ID(9)
ANC EDA
A/P EDA
MASK(1)
MASK(9)
F/F EDA
STATIC
Bit 1
ANC
ANC
(Note 11) I/O 4
(Note 13)
525/27 MHz/Black
EXT CLK Enabled
(Note 13)
Notes
ANC CHECK-
SUM FORCE
MSG TRACK
ANC ID(0)
ANC ID(8)
ANC EDH
A/P EDH
MASK(0)
MASK(8)
F/F EDH
Bit 0
ANC
ANC