LMH0031VS/NOPB National Semiconductor, LMH0031VS/NOPB Datasheet - Page 25

• Manufacturer Part Number: LMH0031VS/NOPB
• Description: IC DESER/DESCRAM DGTL VID 64TQFP
• Manufacturer: National Semiconductor
• Type: Descrambler/Deserializerr

Specifications of LMH0031VS/NOPB

• Applications: SDTV/HDTV
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Input Voltage: 3.3 V
• Supply Voltage (max): 3.45 V
• Supply Voltage (min): 3.15 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• For Use With: SD131EVK - BOARD EVALUATION LMH0031
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *LMH0031VS; *LMH0031VS/NOPB; LMH0031VS

Device Operation
VIDEO CONTROL 0 (register address 55h)
The EXTERNAL V
which enables use of an external VCXO as a substitute for
the internally generated V
within the LMH0031 which provides phase-frequency detec-
tion and control voltage output for the VCXO. An external
loop filter and voltage amplifier are required to interface the
control voltage output to the VCXO frequency control input.
When this function is used, the R
changed from the bias supply output to the control voltage
output of the phase-frequency detector. The V
changes function, becoming the input for the VCXO signal.
Use of this function and required external support circuitry is
explained in the Section Application Information section.
The SYNC DETECT ENABLE bit, when set, enables detec-
tion of TRS characters. This bit is normally set (ON).
The LSB CLIP ENABLE bit, when set, causes the two LSBs
of TRS characters to be set to 00b as described in ITU-R
BT.601. This function is normally set (ON).
The NRZI ENABLE bit, when set, enables data to be con-
verted from NRZI to NRZ. This bit is normally set (ON).
The DE-SCRAMBLE ENABLE bit, when set, enables de-
scrambling of the incoming data according to requirements
of SMPTE 259M or SMPTE 292M. This bit is normally set
(ON).
CAUTION: The default state of this register is 36h. If any of
the normal operating features of the descrambler are turned
off, this register’s default data must be restored to resume
normal device operation.
REFERENCE CLOCK REGISTER (Address 67h)
The Reference Clock register controls operation of the CDR
reference clock source. The CLKEN bit when reset to a
logic-0 enables the oscillator signal to be used by the
CLK
bit is a special application function
CLK
. Additional circuitry is enabled
(Continued)
BB
output function is
CLK
output
25
LMH0031 as a reference. The default state of this bit at
power-on is enabled. In general, this function and bit should
not be disabled. The INT_OSC EN bit enables the internal
crystal oscillator amplifier. By default this bit is a logic-0 and
is therefore inactive at power-on. The device expects an
external 27MHz reference reference clock source to be con-
nected to the XTALi/Ext Clk pin and activated at power-on.
I/O PIN 0 THROUGH 7 CONFIGURATION REGISTERS
(Addresses 0Fh through 16h)
The I/O Pin Configuration Registers are used to map
individual bits of the multi-function I/O port to selected bits of
the Configuration and Control Registers. Table 6 gives the
pin select codes for the Configuration and Control register
functions that may be mapped to the port. Pin[n] Select [5]
controls whether the port pin is input or output. The port pin
will be an input when this bit is set and an output when reset.
Input-only functions may not be configured as outputs and
vice versa. The remaining five Pin[n] Select [4:0] bits iden-
tify the particular Control Register bit to be mapped.
Example: Program, via the AD port, I/O port bit 0 as output
for the CRC Luma Error bit in the control registers.
1. Set ANC/CTRL to a logic-low.
2. Set RD/WR to a logic-low.
3. Present 00Fh to AD[9:0] as the I/O PIN 0 CONFIG
4. Toggle A
5. Present 310h to AD[9:0] as the register data, the bit
6. Toggle A
register address.
address of the CRC Luma Error bit in the control regis-
ters.
CLK
CLK
.
.
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