LMH0031VS/NOPB National Semiconductor, LMH0031VS/NOPB Datasheet - Page 7

• Manufacturer Part Number: LMH0031VS/NOPB
• Description: IC DESER/DESCRAM DGTL VID 64TQFP
• Manufacturer: National Semiconductor
• Type: Descrambler/Deserializerr

Specifications of LMH0031VS/NOPB

• Applications: SDTV/HDTV
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Input Voltage: 3.3 V
• Supply Voltage (max): 3.45 V
• Supply Voltage (min): 3.15 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• For Use With: SD131EVK - BOARD EVALUATION LMH0031
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *LMH0031VS; *LMH0031VS/NOPB; LMH0031VS

Serial Video Data Inputs
BR
t
Parallel Video Data Outputs
f
t
DC
t
Parallel Ancillary / Control Data Inputs, Multi-function Parallel Bus Inputs
f
DC
t
t
t
Parallel Ancillary / Control Data Outputs
t
t
Multi-function Parallel I/O Bus
t
PLL/CDR, Format Detect
t
t
r
VCLK
pd
JIT
ACLK
r
S
H
pd
pd
r
LOCK
FORMAT
Symbol
, t
, t
, t
AC Electrical Characteristics
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (Note 3).
Note 1: “Absolute Maximum Ratings” are those parameter values beyond which the life and operation of the device cannot be guaranteed. The stating herein of
these maximums shall not be construed to imply that the device can or should be operated at or beyond these values. The table of “Electrical Characteristics”
specifies acceptable device operating conditions.
SDI
f
V
A
f
f
Serial Input Data Rate
Rise Time, Fall Time
Video Output Clock
Frequency
Propagation Delay, Video
Clock to Video Data Valid
Duty Cycle, Video Clock
Video Data Output Clock
Jitter
Ancillary / Control Data
Clock Frequency
Duty Cycle, Ancillary Data
Clock
Output Rise Time, Fall
Time
Setup Time, AD
or IO
Hold Time, Rising Edge
A
IO
Propagation Delay, Clock
to Control Data
Propagation Delay, Clock
to Ancillary Data
Rise Time, Fall Time
Lock Detect Time
Format Detect Time
CLK
N
N
to AD
to A
Parameter
CLK
N
or A
Rising Edge
N
CLK
to A
to
CLK
SMPTE 259M, Level C
SMPTE 259M, Level D
SMPTE 344M
SMPTE 292M
SMPTE 292M
20%–80%, SMPTE 259M
Data Rates
20%–80%, SMPTE 292M
Data Rates
SMPTE 259M, 270M
SMPTE 267M, 360M
SMPTE 344M, 540M
SMPTE 292M, 1,483M
SMPTE 292M, 1,485M
50%–50%
27MHz
36MHz
54MHz
74.25MHz
ANC Data clock
(Note 7)
10%–90%
Control Data Input or I/O
Bus Input
50%–50%
10%–90%
SD Rates (Note 5)
HD Rates (Note 5)
All Rates
Conditions
BPS
BPS
BPS
BPS
BPS
7
SDI, SDI
V
V
Timing Diagram
V
V
A
IO
Timing Diagram
A
Timing Diagram
IO0–IO7
Timing Diagram
CLK
CLK
CLK
CLK
CLK
CLK
N
Reference
, AD
to DV
to AD
N
, A
N
N
CLK
Min
0.4
1.0
3.0
3.0
1.0
45
74.176
1,483
1,485
74.25
50
27.0
36.0
54.0
11.5
0.32
0.26
Typ
270
360
540
1.0
0.5
2.0
1.4
1.0
0.5
1.5
1.5
1.5
8.5
1.5
50
20
±
5
V
Max
270
1.5
2.0
3.0
3.0
1.0
1.0
55
CLK
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Units
M
ns
MHz
MHz
ms
ns
ps
ns
ns
ns
ns
%
%
BPS
P-P