LMH1982SQE/NOPB National Semiconductor, LMH1982SQE/NOPB Datasheet

IC CLK GEN MULTI RATE VID 32-LLP

LMH1982SQE/NOPB

Manufacturer Part Number
LMH1982SQE/NOPB
Description
IC CLK GEN MULTI RATE VID 32-LLP
Manufacturer
National Semiconductor
Type
Clock Generatorr
Datasheet

Specifications of LMH1982SQE/NOPB

Applications
Displays, Projectors, Receivers
Mounting Type
Surface Mount
Package / Case
32-LLP
For Use With
LMH1982SQEEVAL - BOARD EVAL FOR LMH1982SQE
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
LMH1982SQETR
© 2009 National Semiconductor Corporation
Multi-Rate Video Clock Generator with Genlock
General Description
The LMH1982 is a multi-rate video clock generator ideal for
use in a wide range of 3-Gbps (3G), high-definition (HD), and
standard-definition (SD) video applications, such as video
synchronization, serial digital interface (SDI) serializer and
deserializer (SerDes), video conversion, video editing, and
other broadcast and professional video systems.
The LMH1982 can generate two simultaneous SD and HD
clocks and a Top of Frame (TOF) pulse. In genlock mode, the
device's phase locked loops (PLLs) can synchronize the out-
put signals to H sync and V sync input signals applied to either
of the reference ports. The input reference can have analog
timing from National's LMH1981 multi-format video sync sep-
arator or digital timing from an SDI deserializer and should
conform to the major SD and HD standards. When a loss of
reference occurs, the device can default to free run operation
where the output timing accuracy will be determined by the
external bias on the free run control voltage input.
The LMH1982 can replace discrete PLLs and field-pro-
grammable gate array (FPGA) PLLs with multiple voltage
controlled crystal oscillators (VCXOs). Only one 27.0000 MHz
VCXO and loop filter are externally required for genlock
mode. The external loop filter as well as programmable PLL
parameters can provide narrow loop bandwidths to minimize
jitter transfer. HD clock output jitter as low as 40 ps peak-to-
peak can help designers using FPGA SerDes meet stringent
SDI output jitter specifications.
The LMH1982 is offered in a space-saving 5 mm x 5 mm 32-
pin LLP package and provides low total power consumption
of about 250 mW (typical).
Typical Video Genlock Block Diagram
300524
LMH1982
Features
Applications
Two simultaneous LVDS output clocks with selectable
frequencies and Hi-Z capability:
— SD clock: 27 MHz or 67.5 MHz
— HD clock: 74.25 MHz, 74.25/1.001 MHz, 148.5 MHz or
Low-jitter output clocks may be directly connected to an
FPGA serializer to meet SMPTE SDI jitter specifications
Top of Frame (TOF) pulse with programmable output
format timing and Hi-Z capability
Two reference ports (A and B) with H and V sync inputs
Supports cross-locking of input and output timing
External loop filter allows control of loop bandwidth, jitter
transfer, and lock time characteristics
Free run or Holdover operation on loss of reference
User-defined free run control voltage input
I
3.3V and 2.5V supplies
Video genlock and synchronization
FPGA SDI SerDes recovered clock generation
Triple rate 3G/HD/SD-SDI SerDes
Video capture, conversion, editing and distribution
Video displays and projectors
Broadcast and professional video equipment
2
C interface and control registers
148.5/1.001 MHz
March 29, 2008
www.national.com
30052407

Related parts for LMH1982SQE/NOPB

LMH1982SQE/NOPB Summary of contents

Page 1

... SDI output jitter specifications. The LMH1982 is offered in a space-saving 32- pin LLP package and provides low total power consumption of about 250 mW (typical). Typical Video Genlock Block Diagram © 2009 National Semiconductor Corporation LMH1982 Features ■ Two simultaneous LVDS output clocks with selectable frequencies and Hi-Z capability: — ...

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Functional Block Diagram Typical Loop Filter Topology Ordering Information Package Part Number LMH1982SQ 32-Pin LLP LMH1982SQE LMH1982SQX www.national.com Package Marking Transport Media 1k Units Tape and Reel L1982SQ 250 Units Tape and Reel 4.5k Units Tape and Reel 2 30052403 ...

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Connection Diagram Top View 32-Pin LLP 3 30052402 www.national.com ...

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Pin Descriptions Pin No. Pin Name – 1 VC_FREERUN 2, 10, 18, 22, 26 21, 27, 28 HREF_A 5 VREF_A 6 REF_SEL 7 HREF_B 8 VREF_B C_ENABLE 14 GENLOCK 15 ...

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General Description .............................................................................................................................. 1 Features .............................................................................................................................................. 1 Applications ......................................................................................................................................... 1 Typical Video Genlock Block Diagram ..................................................................................................... 1 Functional Block Diagram ...................................................................................................................... 2 Typical Loop Filter Topology .................................................................................................................. 2 Ordering Information ............................................................................................................................. 2 Connection Diagram ............................................................................................................................. 3 Pin Descriptions ................................................................................................................................... 4 ...

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Genlock And Input Reference Control Registers .................................................................. 26 9.2 Genlock Status And Lock Control Register ......................................................................... 26 9.3 Input Control Register ...................................................................................................... 26 9.4 PLL 1 Divider Register ..................................................................................................... 27 9.5 PLL 4 Charge Pump Current Control Register ..................................................................... ...

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... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. ESD Tolerance (Note 2) Human Body Model Machine Model Supply Voltage Supply Voltage Input Voltage Range (any input) Electrical Characteristics Unless otherwise specified, all limits are guaranteed for T perature extremes ...

Page 8

Symbol Parameter I Output Hi-Z Leakage Current OZ t Rise Time R t Fall Time F t TOF Output Delay Time (Note D_TOF 9) Clock Outputs (Pins 19, 20, 23, 24) Jitter 27 MHz TIE Peak-to-Peak SD Output Jitter (Note ...

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Note 4: Electrical Table values apply only for factory testing conditions at the temperature indicated. No guarantee of parametric performance is indicated in the electrical tables under conditions different than those tested. Note 5: Typical values represent the most likely ...

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Typical Performance Characteristics Test conditions 3.3V 2.5V, Genlock mode, outputs initialized. H sync and V sync signals to REF_A inputs are from DD VDD the LMH1981 sync separator, which receives an analog video reference signal from ...

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TOF Output Delay Using 27 MHz TOF Clock Note 16: GNLK = 1, REF_DIV_SEL = 1, FB_DIV = 1716, SD_FREQ = 0, TOF_CLK = 0, TOF_PPL = 1716, TOF_LPFM = 525, REF_LPFM = 525, TOF_OFFSET = 262; all other ...

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Supported Standards and Timing Formats Table 1 lists the known supported standard timing formats and includes the relevant parameters that can be used to configure the LMH1982 for the input reference and output timing. For the related programming instructions, see ...

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INPUT TIMING PARAMETERS Format PLL 1 PLL 1 Reference Feedback Divider 1 Divider 1 800 1080i/60 [5] [4000] 1080i/59.94 5 4004 1 960 1080i/50 [5] [4800] 48 kHz AES 2 1125 sample clock 1. The PLL 1 reference divider value ...

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... Jitter using the LMH1982 and Virtex-5 GTP Transmitter • AN-1841: LMH1982 Evaluation Board User Guide The LMH1982SQEEVAL Evaluation Board can be ordered from National Semiconductor's website. 3.0 MODES OF OPERATION The mode of operation describes the operation of PLL 1, which can operate in either Free Run mode or Genlock mode depending on the GNLK bit setting ...

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Program the output clock frequency for the desired output format. Refer to section 5.1 Programming The Output Clock Frequencies. 2. Program the output TOF timing for the desired output format. Refer to section 5.2 Programming The Output Format Timing. ...

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I 2 C_RSEL = 0 (register 00h). The reference signals should be 3.3V LVCMOS signals within the input voltage range specified in the Electrical Character- istics ...

Page 17

TABLE 5. HD Clock Frequency Selection HD_CLK (MHz) HD_FREQ Register 08h 74.25 0h 74.25/1.001 1h 148.5 2h 148.5/1.001 3h 5.2 Programming The Output Format Timing When PLL 1 is stable and locked to the input reference, the output format timing ...

Page 18

FIGURE 3. Functional Block Diagram – TOF Generation and Output Initialization Circuitry www.national.com 18 30052437 ...

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Output TOF Clock The TOF pulse is derived from a counter chain, which re- ceives either output clock (SD_CLK or HD_CLK) from a 2:1 MUX block, as shown in Figure 3. The TOF clock from the MUX can be ...

Page 20

REF_LPFM = Reference Format Total Lines per Frame 5.2.4 Input-Output Frame Rate Ratio The input-output frame rate ratio is also used for resetting the internal counters for output initialization. The ratio is the Input Frame Rate / Output Frame Rate, ...

Page 21

VCXO, which may be in Free Run or Holdover operation. To disable output alignment to an arbitrary reference frame when the reference is reapplied, set EN_TOF_RST = 0 before the reference returns. After ...

Page 22

TABLE 7. Summary of Genlock Status Bits and Flag Outputs Mode Control Bits Conditions GNLK Genlock mode, Reference valid, PLLs locking Genlock mode, Reference valid, PLLs locked Genlock mode, Reference lost, Free Run operation Genlock mode, Reference lost, Holdover operation ...

Page 23

Loop Response Optimization Tips The need to support various input reference formats will usu- ally require a diverse range of PLL divider values, which can each yield a different loop response assuming all other PLL parameters are kept the ...

Page 24

Read Sequence Read sequences are comprised of two I is the address access transfer, which consists of a write se- quence that transfers only the address to be accessed. The second is the data read transfer, which starts at ...

Page 25

INTERFACE CONTROL REGISTER DEFINITIONS TABLE Interface Control Register Map Register Default D7 D6 Address Data 00h A3h GNLK_I 2 C GNLK 01h 86h 02h 00h RSV RSV 03h 01h RSV RSV 04h ...

Page 26

Genlock And Input Reference Control Registers Register 00h Bits 2-0: H Input Error Max Count (H_ERROR) The H_ERROR bits control the reference detector's error threshold, which determines the maximum number of missing H sync pulses before indicating a LOR. ...

Page 27

MHz input and H sync inputs. Alternatively, it's possible to use an external counter circuit to divide the 27 MHz clock to a lower frequency (e.g. like H sync) input, so ...

Page 28

Bits 7-0: TOF Reset (TOF_RST) This register contains the 8 LSBs of TOF_RST. When PLL 1 is phase locked to the reference, both H sync and V sync in- puts are used to reset the frame-based counters used for output ...

Page 29

For more information on setting the loop response, see section 7.0 LOOP RESPONSE . To minimize lock time, using a large or maximum I result in faster PLL settling time due to a wider loop band- width. ...

Page 30

TYPICAL SYSTEM BLOCK DIAGRAMS FIGURE 9. Analog Reference Genlock for Triple-rate SDI Video FIGURE 10. SDI Reference Genlock for Triple-rate SDI Video www.national.com 30 30052407 30052408 ...

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FIGURE 11. Triple-rate SDI Loop-through FIGURE 12. Combined Genlock or Loop-through for Triple-rate SDI Video 31 30052409 30052410 www.national.com ...

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Physical Dimensions www.national.com inches (millimeters) unless otherwise noted 32-Pin LLP NS Package Number SQA32A 32 ...

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Notes 33 www.national.com ...

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... For more National Semiconductor product information and proven design tools, visit the following Web sites at: Products Amplifiers www.national.com/amplifiers Audio www.national.com/audio Clock and Timing www.national.com/timing Data Converters www.national.com/adc Interface www.national.com/interface LVDS www.national.com/lvds Power Management www.national.com/power Switching Regulators www.national.com/switchers LDOs www.national.com/ldo LED Lighting www ...

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