MAX9400 Maxim, MAX9400 Datasheet
MAX9400
Related parts for MAX9400
MAX9400 Summary of contents
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... A variety of input and output terminations are offered for maximum design flexibility. The MAX9400 has open inputs and open emitter outputs. The MAX9402 has open inputs and 50Ω series outputs. The MAX9403 has 100Ω ...
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... Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS ( 2.375V to 5.5V, MAX9400/MAX9403 outputs terminated with 50Ω ± 3.3V ...
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... V - 0.2V ILD 3.3V IHD CC CONDITIONS MAX9400/MAX9403 t PLH1 SEL = high, Figure 3 t MAX9402/MAX9405 PHL1 MAX9400/MAX9403 t PLH2 SEL = low, Figure 4 t MAX9402/MAX9405 PHL2 t SEL = high SKD1 t SEL = low SKD2 ≥ 500mV, SEL = low ≥ 400mV, SEL = high IN(MAX) ...
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... Quad Differential LVECL/LVPECL Buffer/Receivers ( 3.3V, MAX9400, outputs terminated with 50Ω ± input transition time = 125ps (20% to 80%), V SUPPLY CURRENT ( vs. TEMPERATURE -40 - TEMPERATURE (°C) IN-TO-OUT PROPAGATION DELAY vs. TEMPERATURE 355 350 345 340 335 330 ...
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PIN NAME 1, 8,11, Positive Supply Voltage. Bypass 17, 24, 30 capacitors as close to the device as possible with the smaller value capacitor closest to the device. Noninverting Differential Select Input. Setting SEL = high and ...
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... A variety of input and output terminations are offered for maximum design flexibility. The MAX9400 has open inputs and open-emitter outputs. The MAX9402 has open inputs and 50Ω series outputs. The MAX9403 has 100Ω ...
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... Minimize skew by matching the electrical length of the traces INPUT VOLTAGE DEFINITION Figure 1. Input and Output Voltage Definitions IN_ IN_ MAX9400/MAX9402 MAX9400/MAX9403 Figure 2. Input and Output Configurations _______________________________________________________________________________________ Quad Differential LVECL/LVPECL TRANSISTOR COUNT: 713 PROCESS: Bipolar V (MAX) IHD (MAX) ILD ...
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Quad Differential LVECL/LVPECL Buffer/Receivers IN_ IN_ OUT_ OUT_ DIFFERENTIAL OUTPUT WAVEFORM OUT_ - OUT_ Figure 3. IN-to-OUT Propagation Delay and Transition Timing Diagram CLK CLK t H IN_ IN_ OUT_ OUT_ Figure 4. CLK-to-OUT Propagation Delay Timing Diagram 8 _______________________________________________________________________________________ ...
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... IN_ 100Ω IN_ 1kΩ 1/4 MAX9400/MAX9402 Figure 5. Input Bias Circuits for Unused Inputs Pin Configurations (continued) TOP VIEW * SEL 2 SEL 3 MAX9400 CLK 4 MAX9402 MAX9403 CLK 5 MAX9405 EN 6 *EXPOSED PADDLE QFN-EP* *EXPOSED PADDLE AND CORNER PINS ARE CONNECTED TO V _______________________________________________________________________________________ ...
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Quad Differential LVECL/LVPECL Buffer/Receivers IN0 IN0 IN1 IN1 IN2 IN2 IN3 IN3 CLK CLK SEL SEL ______________________________________________________________________________________ ...
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... For the latest package outline information www.maxim-ic.com/packages.) ______________________________________________________________________________________ Quad Differential LVECL/LVPECL Buffer/Receivers Package Information PACKAGE OUTLINE, 32L TQFP, 5x5x1.0mm 1 B 21-0110 2 PACKAGE OUTLINE, 32L TQFP, 5x5x1.0mm ...
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... Quad Differential LVECL/LVPECL Buffer/Receivers (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information www.maxim-ic.com/packages. 12 ______________________________________________________________________________________ Package Information (continued) ...
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... For the latest package outline information www.maxim-ic.com/packages. Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. ...