74VHC125M Fairchild Semiconductor, 74VHC125M Datasheet

IC BUFF TRI-ST QD N-INV 14SOIC

74VHC125M

Manufacturer Part Number
74VHC125M
Description
IC BUFF TRI-ST QD N-INV 14SOIC
Manufacturer
Fairchild Semiconductor
Series
74VHCr
Datasheet

Specifications of 74VHC125M

Logic Type
Buffer/Line Driver, Non-Inverting
Number Of Elements
4
Number Of Bits Per Element
1
Current - Output High, Low
8mA, 8mA
Voltage - Supply
2 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
14-SOIC (3.9mm Width), 14-SOL
Logic Family
74VHC
Number Of Channels Per Chip
Quad
Polarity
Non-Inverting
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2 V
Maximum Operating Temperature
85 C
Mounting Style
SMD/SMT
High Level Output Current
- 8 mA
Input Bias Current (max)
4 uA
Low Level Output Current
8 mA
Minimum Operating Temperature
- 40 C
Number Of Lines (input / Output)
3
Output Type
3-State
Propagation Delay Time
11.5 ns @ 3.3 V or 7.5 ns @ 5 V
Logic Device Type
Buffer, Non Inverting
Supply Voltage Range
2V To 5.5V
Logic Case Style
SOIC
No. Of Pins
14
Operating Temperature Range
-40°C To +85°C
Filter Terminals
SMD
Rohs Compliant
Yes
Family Type
74VHC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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©1993 Fairchild Semiconductor Corporation
74VHC125 Rev. 1.4.0
74VHC125
Quad Buffer with 3-STATE Outputs
Features
Ordering Information
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
74VHC125M
74VHC125SJ
74VHC125MTC
High Speed: t
Lower power dissipation: I
T
High noise immunity: V
Power down protection is provided on all inputs
Low noise: V
Pin and function compatible with 74HC125
A
All packages are lead free per JEDEC: J-STD-020B standard.
Order Number
25°C
OLP
PD
3.8ns (Typ.) at V
0.8V (Max.)
NIH
CC
Package
Number
MTC14
V
M14A
M14D
NIL
4 µA (Max.) at
CC
28% V
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150"
Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
4.4mm Wide
5V
CC
(Min.)
General Description
The VHC125 contains four independent non-inverting
buffers with 3-STATE outputs. It is an advanced high-
speed CMOS device fabricated with silicon gate CMOS
technology and achieves the high-speed operation simi-
lar to equivalent Bipolar Schottky TTL while maintaining
the CMOS low power dissipation.
An input protection circuit insures that 0V to 7V can be
applied to the input pins without regard to the supply
voltage. This device can be used to interface 5V to 3V
systems and two supply systems such as battery
backup. This circuit prevents device destruction due to
mismatched supply and input voltages.
Package Description
December 2007
www.fairchildsemi.com

Related parts for 74VHC125M

74VHC125M Summary of contents

Page 1

... Order Number Number 74VHC125M M14A 74VHC125SJ M14D 74VHC125MTC MTC14 Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. All packages are lead free per JEDEC: J-STD-020B standard. ©1993 Fairchild Semiconductor Corporation 74VHC125 Rev. 1.4.0 General Description ...

Page 2

... Connection Diagram Pin Description Pin Names Inputs Outputs n ©1993 Fairchild Semiconductor Corporation 74VHC125 Rev. 1.4.0 Logic Symbol Function Table Description HIGH Voltage Level L LOW Voltage Level Z HIGH Impedance X Immaterial 2 IEEE/IEC Inputs Output www.fairchildsemi.com ...

Page 3

... OPR Input Rise and Fall Time 3.3V ± 0. 5.0V ± 0.5V CC Note: 1. Unused inputs must be held HIGH or LOW. They may not float. ©1993 Fairchild Semiconductor Corporation 74VHC125 Rev. 1.4.0 Parameter (1) Parameter 3 Rating –0.5V to +7.0V –0.5V to +7.0V –0. 0.5V CC –20mA ±20mA ±25mA ± ...

Page 4

... OL (2) V Quiet Output Minimum OLV Dynamic V OL (2) V Minimum HIGH Level IHD Dynamic Input Voltage (2) V Maximum HIGH Level ILD Dynamic Input Voltage Note: 2. Parameter guaranteed by design. ©1993 Fairchild Semiconductor Corporation 74VHC125 Rev. 1.4.0 (V) Conditions Min. 1.50 0 –50µA 1 2.9 4.4 I – ...

Page 5

... PD current consumption without load. Average operating current can be obtained by the equation: I (Opr.) C • V • ©1993 Fairchild Semiconductor Corporation 74VHC125 Rev. 1.4.0 V (V) Conditions CC 3.3 ± 0.3 C 15pF L C 50pF L 5.0 ± ...

Page 6

... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifi ...

Page 7

... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifi ...

Page 8

... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifi ...

Page 9

... TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended exhaustive list of all such trademarks. ® ACEx Build it Now™ CorePLUS™ CROSSVOLT™ CTL™ Current Transfer Logic™ ...

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