TB1328FG Toshiba, TB1328FG Datasheet

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TB1328FG

Manufacturer Part Number
TB1328FG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TB1328FG

Function
Programmable audio/video switch and frequency detection
Features
CVBS, S-Video or YcbrCr/RGB or D-connector, auto sync processor, pre-filter, dummy HD/VD output
Operating Voltage
9V,5V
Package
QFP64 (lead-free)
Audio SW, Video SW, Sync Separation and H/V Frequency Counter IC for TVs
AD converter, sync separations and an H/V format detector for TV
signals.
occupied by LCR filters and to the simplification of designs in analog
interfaces.
which various functions can be controlled.
Features
AUDIO SW BLOCK
・ Audio (L/R) inputs: 8 channels
・ Audio (L/R) output: 2 channels
VIDEO SW BLOCK
・ CVBS inputs
・ Y/C inputs
・ Component video inputs (co-use as RGB inputs)
・ Output: 1 channel (Y/CVBS/G,C/Cb/B,Cr/R)
・ Monitor output
VIDEO BLOCK
・ Gain switching: -3 dB / 0 dB / +3 dB(Output: 1 channel)
・ GCA-Amp for only CVBS: 4 to –6dB,6bit(Output: 1 channel)
・ Bandwidth filter: pre-filter for ADC; 5 to 46 MHz variable(Output: 1 channel)
・ +6dB Amp, No pre-filter (Monitor output)
SYNC SEPARATION BLOCK
・ Supports 525/30p/60i/60p, 625/50i/50p, 750/50p/60p, 1125/24p/24sf/25p/30p/50i/60i/50p/60p, 1250/50i,
・ HD/VD input: 1 channel; positive and negative input acceptable
・ HD/VD output: positive and negative output selectable
・ Masking pseudo-sync for copyguard signal
OTHERS
・ Line detector for Japanese D-pin
・ S2, S1, insertion detection for S-pin
・ Horizontal and vertical frequency counter
・ Input signal format detection circuit
・ No-input detection
・ Automatic sync process switching mode
・ Programmable number of video inputs
The TB1328FG includes Audio and video SW blocks, pre-filters for
The TB1328FG contributes to a reduction in the proportion of PCB
The TB1328FG is equipped with an I
VGA @60, SVGA@60, XGA@60, SXGA@60, UXGA@60
(SY/Y/C/CVBS)
TOSHIBA BiCMOS Integrated Circuit Silicon Monolithic
2
CBUS interface through
TB1328FG
1
Weight: 0.34 g (typ.)
LQFP64-P-1010-0.50A
TB1328FG
2006-11-13

TB1328FG Summary of contents

Page 1

... Audio SW, Video SW, Sync Separation and H/V Frequency Counter IC for TVs The TB1328FG includes Audio and video SW blocks, pre-filters for AD converter, sync separations and an H/V format detector for TV signals. The TB1328FG contributes to a reduction in the proportion of PCB occupied by LCR filters and to the simplification of designs in analog interfaces. 2 The TB1328FG is equipped with an I which various functions can be controlled ...

Page 2

... Block Diagram 1 (simplified complete diagram) This IC will not function with non-standard signals such as weak signals, ghost signals, etc. Some of the functional blocks, circuits, or constants in the block diagram may be omitted or simplified for explanatory purposes. 2 TB1328FG 2006-11-13 ...

Page 3

... Block Diagram 2 (Video block) Some of the functional blocks, circuits, or constants in the block diagram may be omitted or simplified for explanatory purposes. OUT" "YCbCr as R/G/B as Cb/ CVBS "CbCr PIN1" "CbCr PIN2" "CbCr PIN3" 3 TB1328FG "MON OUT" "YCbCr1 OUT" 2006-11-13 ...

Page 4

... AL7 IN 59 ATT AR8 IN 61 ATT AL8 IN 63 ATT Some of the functional blocks, circuits, or constants in the block diagram may be omitted or simplified for explanatory purposes. Total 0dB Total 0dB Total 0dB Total 0dB 4 TB1328FG 5 AR1 OUT 3 AL1 OUT 15 AR2 OUT 13 AL2 OUT 2006-11-13 ...

Page 5

... POL POL DET DET H-C/D H/V H DUMMY SEP V-C/D V SEP V DUMMY “HV DUMMY” H/V SEP V SEP "HV DET" H/V SEP "SIG SW" SYNC FILTER 5 TB1328FG REG 3.3V (typ.) XO clock TEST POL POL HD WIDTH "HV OUT" TEST I2CBUS NO-SIGNAL “SIG DET” DET 10 2006-11-13 Vdd (3.3V) 21 Vss 19 ...

Page 6

... DC6(LINE1-1) AL3 IN Cr1/R1 IN AR4 IN Cb1/B1 IN AL4 IN Y1/G1 IN AR5 IN SY1 IN AL5 IN SC1 IN AR6 IN CVBS3 IN AL6 IN Cr2/ Vcc (9V) SYNC FILTER V/S Vcc (5V) CVBS/Y/G OUT 6 TB1328FG AR2 OUT DC2(S1) AL2 OUT V/S GND SYNC2 IN VD OUT HD OUT Cr/R OUT AR1 OUT Cb/B OUT AL1 OUT DC1(S2) 2006-11-13 ...

Page 7

... TB1328FG Input Signal/Output Signal 3.3 V (typ.) − 5.0 V (typ.) − 9.0 V (typ.) − Sync tip level: 2.3 V (typ.) Y/CVBS signal amplitude: 1.0 Vp-p (with sync) 2.9 V bias (typ.) Burst signal amplitude: 0.3 Vp-p Sync tip level: 2.3 V (typ.) Bias level: 2.9 V (typ.) Y/G/CVBS signal amplitude: 1 ...

Page 8

... This pin is also used as test signal output pin for shipping only. Interface Circuit 7 36 200Ω TB1328FG Input Signal/Output Signal Sync tip level: 2.3 V (typ.) Bias level: 2.9 V (typ.) Cr/R signal amplitude: 0.7 Vp-p (without sync) CVBS/Y signal amplitude: 1.0 Vp-p (with sync) 2.9 V bias (typ.) Cr/R signal amplitude: ...

Page 9

... Use the leading edge only. A filter pin for sync detection. 10 SYNC FILTER Connect a capacitor between this pin and GND. Interface Circuit TB1328FG Input Signal/Output Signal Sync tip level: 1.8 V (typ.) or 1Vp-p 1.45 V bias (typ.) or AC: - (typ.) AC (typ.) or − ...

Page 10

... SDA SDA pin for I CBUS SCL SCL pin for I CBUS. Interface Circuit 7 5kΩ 17 50Ω ACK 19 7 5kΩ TB1328FG Input Signal/Output Signal − 1.3 V (typ 2.1 V (typ 1.3 V (typ 2.1 V (typ.) 2006-11-13 ...

Page 11

... V IN V-SYNC-W V FORMAT HV-OUT FORMAT DC3(27Pin) DC2(14PIN) DC7(49Pin) DC6(34Pin) ∗ ∗ DC10(55Pin) S3(48Pin) S2(44Pin) S1(38Pin) Cr2in SC1in Cb1in H FREQ DET V FREQ DET 11 TB1328FG D1 D0 PRESET 00000000 (0) (0) 00000000 00000000 00000000 00000000 CbCr GAIN 00000000 CLAMP2 CLAMP1 00000000 00000000 AU1 OUT 00010001 (0) ...

Page 12

... NOTE: If GCA SW is GCA OFF, set GCA Gain to minimum. After setting D7=1(SA:04H,12H,13H,14H) and GCA Gain to MIN(3FH), set D7=0(SA:04H,12H,13H,14H). Function 1: ON (1/2 fc for Cb/Cr (bypass) 1: MIX (Y+C) 1: HIGH 1111111: MAX (high) 1:GCA V timing ON 1:GCA ON 111111: Gain MIN (low) 12 TB1328FG Preset Value OFF (0) Mute (0000) OFF (0) OFF (0) Mute (0000) ...

Page 13

... AL/AR6 (pins 47/45) 1000: AL/AR8 (pins63/61) Function 10: +3dB 01: -3dB 11: Not available 10: +3dB 01: -3dB 11: Not available 0001: AL/AR1 (pins28/26) 0011: AL/AR3 (pins35/33) 0101: AL/AR5 (pins43/41) 0111: AL/AR7 (pins59/57) 1001~1111: Not available 13 TB1328FG Preset Value 0dB (00) Cb/Cr input (0) Cb/Cr input (0) Cb/Cr input (0) SYNC TIP (0) SYNC TIP (0) all 0 ...

Page 14

... FORMAT and H, V FREQ DET. 0: OFF Switches the mask mode for pseudo-sync. PS MASK 0: ON (Normal) (1)OFF mode is used for “Sync on G” input. Function 11: HIGH OFF (for “Sync on G”) 14 TB1328FG Preset Value LOW (00) OFF (0) OFF (0) OFF (0) ON (0) 2006-11-13 ...

Page 15

... NOTE: The VD output does not synchronize with input sync when A-SYNC = OFF and when a sync is input. Function 1: Full detection 1: NARROW 1: Negative 1: HD/VD-IN (pins 23/22) 1: HD/VD-IN (pins 23/22 (Dummy HD output when no-input (Dummy VD output when no-input) 15 TB1328FG Preset Value 50/60 only (0) WIDE (0) Positive (0) SYNC (0) SYNC2-IN ...

Page 16

... TEST modes for shipping test. Set all to zero. Function 1111: 62 counts (2 counts / step) 111: 30 counts (2 counts / step) 1: Reset 1: SYNC1-IN (pin 25) 01: 15 kΩ 11: 6 kΩ 01: 0.80 V 11: 1. TB1328FG Preset Value 15.625 kHz (00000) 32 counts (0000) 16 counts (000) 1 count (0000) 1 count (0000) Normal ...

Page 17

... Hz (525i) 00011: 31.5 kHz (525p, VGA @60 Hz) 00101: 33.75 kHz (1125/60i) 00111: 45 kHz (750/60p, XGA @60 Hz) 01001: 37.9 kHz (SVGA @60 Hz) 10001: 27 kHz (1125/24p) 10011: 33.75 kHz (1125/30p) 17 TB1328FG 0011: 33.75 kHz 0111: 64/67.5 kHz 011 2006-11-13 ...

Page 18

... Function 01: Mid (2.2 V) 10: Undefined 01: ---- 10: ---- 01: 750 (720) 10: ---- 01: ---- 10: ---- 01: 4:3 letter box 10: ---- 01: 4:3 letter box 10: ---- 1: Open (connected) 01001111 less 10011001 less -4 ) [Hz] 11111111: over 85kHz 11111111: over 85kHz 18 TB1328FG 11: High (5 V) 11: Not-connected 11: 1125 (1080) 11: progressive 11: 16:9 11: 16:9 2006-11-13 ...

Page 19

... Y2 (pin 52) + Cb2 (pin 50) Y3 (pin 58) ∗ ∗ Y3 (pin 58) + Cb3 (pin 56) ∗ ∗ Not available ∗ ∗ Cr1 (pin 36) ∗ ∗ Cr3(pin 54) ∗ ∗ Not available 19 TB1328FG Available input YCbCr CVBS YC (pin 6) RGB Mute Mute y y Mute y y Mute y Mute ...

Page 20

... Normal application V- SYNC Leading edge V- SYNC Leading edge 1125/60p signal SYNC-IN (Y-IN) HD-OUT (HD WIDTH=1) 0.7us (typ) HD-OUT (HD WIDTH=0) 1.7us (typ) 2.0 to 5.0 Vp-p Input HD/VD-IN 20 TB1328FG Trailing edge with a jitter Trailing edge with a jitter 1uF/4.7uF pin 22,23 or HD/VD-IN 5.6kΩ For large input application 2006-11-13 ...

Page 21

... Signal Unknown Signal Known: The status indicates not No input the current condition but the last detected format. Fig. The signal route when A-SYNC = OFF 21 TB1328FG HD, VD outputs The separated sync as input The separated sync as input Dummy HD and VD, of which the frequency ...

Page 22

... For “Sync on G” signal, HD-OUT is not output during V-sync period because there is no H-sync during V-sync period TB1328FG 2006-11-13 ...

Page 23

... When N1 ≦ Nmin, N1 ≧ Nmax, and when N3 ≧ Nreset, SIG DET returns 0. Where, Nreset: the number set by SIG RESET N N3: the number of condition where “N1 ≦ Nmin and N1 ≧ Nmax” is detected Determine the use of no-input detection following sufficient evaluations using a prototype TV set. Fig. block diagram of no-input detection 23 TB1328FG 2006-11-13 ...

Page 24

... TB1328FG "S1~6" DEC HEX Freqency[Hz]Freqency[Hz] V-det=0 V-det=1 ~ No Input ~ 111 6F No Input 31.5 112 70 No Input 31 ...

Page 25

... TB1328FG DEC HEX Freqency[kHz] Freqency[kHz] Sync IN HD/VD IN 133 85 44.33 44.33 134 86 44.67 44.67 135 87 45.00 45.00 136 88 45.33 45.33 137 89 45.67 45.67 ~ 166 A6 55 ...

Page 26

... Bin 000000 001101 011010 100001 100111 110100 111111 Dec 0 Hex 00 -3dB CVBS GCA output 0.7Vp-p Output Level(Vp-p) GAIN Typ.(dB) 1 1.2 1.4 Input Level Typ 0.881 0.9998 1.1015 1.3221 0.7 0.7 0.7 0.7 0 TB1328FG 100IRE 768LSB 256LSB 1.6 Max 1.4 0 2006-11-13 ...

Page 27

... SW = high, BANDWIDTH = max -50 0.1 1 Fig. Typical pre-filter frequency characteristics high low high, fc HALF = low, fc HALF = Fig. Typical cutoff frequency characteristics of pre-filter (-3 dB point) 10 Frequency [MHz 100 BANDWIDTH data 27 TB1328FG 100 120 127 2006-11-13 ...

Page 28

... Instead of connecting a crystal oscillator possible to input an external CW (Continual Wave) into pin 28 through a capacitor as below. The required specs on the CW are as follows. Input frequency (fundamental): 3.579545MHz +/- 50ppm Input amplitude: 1.0Vp-p +/- 0.5Vp high low high, fc HALF = low, fc HALF = BANDWIDTH data 20 XTAL 220pF 28 TB1328FG 100 120 127 2006-11-13 ...

Page 29

... Procedure 2 SY2 IN 60 Procedure 1 AR8 IN 61 Procedure 1 SC2 IN 62 Procedure 2 AL8 IN Procedure 1 63 MONITOR OUT 64 Procedure 1 − − Procedure 1 29 TB1328FG Procedure Procedure 1 Procedure 1 Procedure 1 Procedure 1 Procedure 1 Procedure 1 Procedure 1 Procedure 1 Procedure 1 Procedure 1 Procedure 1 Procedure 2 Procedure 1 Procedure 2 Procedure 1 Procedure 2 Procedure 1 Procedure 2 Procedure 1 ...

Page 30

... Start condition Bit Transmission SDA SCL SDA must not be changed Acknowledgement SDA from transmitter SDA from receiver SCL from master S 2 CBUS A0 W 0/1 Stop condition SDA may be changed High impedance at bit Clock pulse for acknowledgement 30 TB1328FG P Low impedance at bit 9 only 9 2006-11-13 ...

Page 31

... HD;STA − t 1.3 LOW − t 0.6 HIGH − t 0.6 SU;STA − HD;DAT − t 100 SU;DAT − t 0.6 SU;STO − t 1.3 BUF 31 TB1328FG Transmit data 8-bit Max. Unit 1.1 V V/S-Vcc V − V 0.4 V µ 400 kHz − µs − µs − µs − µs − ns − ...

Page 32

... Symbol 9V Vcc V CCmax9 5V Vcc V CCmax5 3.3V Vcc V CCmax3 (Note 4) D 1/θja T opr T stg 1388 833 150 Ambient temperature Ta (°C) Figure Curve D 32 TB1328FG Rating Unit 12.0 V 6.0 6.0 GND − 0.3 ~ Vcc + 0.3 V 2.0 Vp-p 1388 mW 11.1 mW/°C − °C −55 ~ 150 °C 2006-11-13 ...

Page 33

... DC detection input voltage S1~6 Pins 38,44,48,50,56,62 SDA input current Pins 17 Remark: Supply power to all Vcc pins (pin 7,16,21). Description Min. 8.5 4.7 3.1 − − − − 0 − 3.5 M 1.4 L GND L GND − 33 TB1328FG Typ. Max. Unit 9.0 9.5 5.0 5.3 V 3.3 3.5 − 1.0 V p-p − 1 MHz - 8 MHz − p-p − 0.7 V p-p - ...

Page 34

... V 29 − − − − − − − − − − − − − TB1328FG 2 CBUS data: preset values) Typ. Max Unit 7.8 10.3 mA 67.9 89.6 9.3 12.7 Min Typ. Max Unit − − 0.1 1.0 1.3 1.6 3.8 4.1 4.4 1.0 1.3 1.6 3.8 4.1 4.4 1.0 1.3 1.6 3.0 3.3 3.6 1.5 1.8 2.1 3.8 4 ...

Page 35

... MONITOR OUT 64 V Test Conditions − 43 − 44 − 45 − 46 − 47 − 48 − 49 − 50 − 51 − 52 − 53 − 54 − 55 − 56 − 57 − 58 − 59 − 60 − 61 − 62 − 63 − TB1328FG Min Typ. Max Unit 4.2 4.4 4.6 2.6 2.9 3.2 4.2 4.4 4.6 2.0 2.3 2.6 4.2 4.4 4.6 2.6 2.9 3.2 − − 0.1 2.6 2.9 3.2 − − 0.1 2.0 2.3 2.6 − − 0.1 V 2.6 2.9 3.2 − − 0.1 2.6 2.9 3.2 4.2 4 ...

Page 36

... FILPASS = 0/1, input = 0.2Vp-p 10 kHz, BANDWIDTH = cnt G+3 G+6 MONITOR OUT Gmin Input = 0.2Vpp 10kHz Gcnt BUS setting Y/CVBS GAIN=-3dB Gmax SY-IN to MONITOR-OUT, No input Gycmy into SC-IN, YC MIX = 1 SC-IN to MONITOR-OUT, No input Gycmc into SY-IN, YC MIX = 1 36 TB1328FG Min Typ Max Unit -1.0 0 1.0 dB ⎯ ⎯ 100 kHz ⎯ 0.02 0.05 % ⎯ ...

Page 37

... NOTE A fdHmin TdL-3 FILPASS = 1, 1 MHz, NOTE A TdL0 TdL+3 FILPASS = 0, GAIN = 00 TdLcnt 1 MHz, NOTE A TdLmin FILPASS = 0, GAIN = 00 TdHcnt 1 MHz, NOTE A TdHmin 37 TB1328FG Min Typ. Max Unit − 80 100 − MHz 80 100 − 80 100 14.0 16 ...

Page 38

... TgdLmin FILPASS = 1, 1 MHz, NOTE A TgdLcnt TgdLmax fgm 0.2 Vp-p input point, NOTE A Gmute 5 MHz sin wave input, NOTE A Gcrschs 5 MHz sin wave input, NOTE A Gcrsins Gcrsync BANDWIDTH=min, NOTE A 38 TB1328FG Min Typ. Max Unit 100 190 220 260 ...

Page 39

... Separated VD-OUT Tvdwodd When 1250i input Tvdweven Tvdwfi Free-run VD-OUT in interlace mode Free-run VD-OUT in progressive Tvdwfp mode Tvdp Except 1250/50i input, NOTE D 1250/50i input, H sync-in to VD-out, Tvdp1250 NOTE D Tvdphv HV OUT = 1, NOTE A 39 TB1328FG Min Typ Max Unit ...

Page 40

... HV FREQ2 = 00111, V DMY = 1 HV FREQ2 = 01000, V DMY = 1, ODD HV FREQ2 = 01000, V DMY = 1, EVEN fvsvga HV FREQ2 = 01001, V DMY = 1 fvsxga HV FREQ2 = 01010, V DMY = 1 fvuxga HV FREQ2 = 01011, V DMY = 1 HV FREQ2 = 10000, V DMY = 1 40 TB1328FG Min Typ. Max Unit − − 15.564 − − 15.701 − − ...

Page 41

... Imnsfil211 SIG DET IMPE = 11, NOTE G Vthns00 SIG DET LVL = 00, NOTE H Vthns01 SIG DET LVL = 01, NOTE H Vthns10 SIG DET LVL = 10, NOTE H Vthns11 SIG DET LVL = 11, NOTE H VdcthLM Pins 1,14,27,29,31,34,49,51,53,55 VdcthMH VdcthS Pins 38,44,48,50,56,62 Imdc Pins 1,14,27,29,31,34,49,51,53,55 41 TB1328FG Min Typ. Max Unit − − 0.4 Vp-p µs 0.5 1.5 2 ...

Page 42

... SYNC FILTER VD OUT HD OUT #7 V/S Vcc (5V) #6 Cr1/R1 OUT AR1 OUT #4 Cb1/B1 OUT AL1 OUT #2 CVBS/Y1/G1 OUT 10kΩ DC1(S2) 0.1μF 42 TB1328FG + + 100μF 100μF 0.01μF 0.01μF AR2 OUT 10kΩ FB OUT 0.1μF AL2 OUT 0.1μF SYNC2 IN 180pF VD OUT HD OUT 0.01μF + 47μ ...

Page 43

... Audio 7 H-SYNC 1.5kΩ V-SYNC 9 8 1.5kΩ S-pin 2 43 TB1328FG + + 100μF 100μF 0.01μF 0.01μF AU Vcc (9V) AR2 OUT 0;1μF #14 DC2(S1) 10kΩ AR2 OUT AL2 OUT AL2 OUT V/S GND #11 0.1μF SYNC2 IN #10 180pF SYNC FILTER ...

Page 44

... The application circuits shown in this document are provided for reference purposes only. Thorough evaluation is required especially in the mass production design phase. Toshiba dose not grant the use of any industrial property rights with these examples of application circuits D-SUB15 44 TB1328FG D-SUB15 2006-11-13 ...

Page 45

... In such cases, the signal switcher and the video circuits of the TB1328FG can be used. Exceptionally, “the no signal detection” can be also used for those signals. ...

Page 46

... Package dimensions LQFP64-P-1010-0.50A Weight: 0.34 g (Typ.) 46 TB1328FG Unit: mm 2006-11-13 ...

Page 47

... No license is granted by implication or otherwise under any patents or other rights of TOSHIBA or the third parties. 021023_C • The products described in this document are subject to the foreign exchange and foreign trade control laws. 021023_E 021023_D 021023_B 060106_Q 47 TB1328FG 060116EBA 2006-11-13 ...

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