TMPM380FWDFG Toshiba, TMPM380FWDFG Datasheet - Page 40
TMPM380FWDFG
Manufacturer Part Number
TMPM380FWDFG
Description
Manufacturer
Toshiba
Datasheet
1.TMPM380FWDFG.pdf
(700 pages)
Specifications of TMPM380FWDFG
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
128K
Rom Type
Flash
Ram (kbytes)
12K
Number Of Pins
100
Package
QFP(14×20)
Vcc
5V
Cpu Mhz
40
Ssp (ch) Spi
2
I2c/sio (ch)
2
Uart/sio (ch)
5
Usb
-
Can
-
Ethernet
-
External Bus Interface
N
Cs/wait Controller (ch)
-
Dma Controller
2
10-bit Da Converter
-
10-bit Ad Converter
-
12-bit Ad Converter
18
16-bit Timer / Counter
8
Motor / Igbt Control
Y
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
Y
Clock Gear
Y
Low-power Hold Function
-
Remote Control Interface
Y
Hardware Cec Controller
-
Comparators
-
Low-voltage Detector
Y
Etm Hardware Trace
2-bit
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6.3
6.3.1
6.3.2
Fig. 6-1 shows the clock system diagram. Each clock is defined as follows.
The high-speed clock fgear and the prescaler clock ΦT0 are dividable.
•
•
Reset initializes the clock configuration as follows.
Reset initializes all the clock configurations to be the same as fosc2.
Reset configures fsys to high-speed oscillator2 (internal)..
Clock Control
fosc1
fosc2
fs
fosc
fpll
fc
fgear
fsys
fperiph : Clock specified by CGSYSCR<FPSEL1:0>
ΦT0
High-speed clock: fc, fc/2, fc/4, fc/8, fc/16
Prescaler clock: fperiph, fperiph/2, fperiph/4, fperiph/8, fperiph/16,fperiph/32
High-speed oscillator2 (Internal)
High-speed oscillator1 (External) : OFF (stop) X1,X2
Low-speed oscillator (External)
PLL (phase locked loop circuit)
High-speed clock gear
Clock System Block Diagram
Initial Values after Reset
: Clock input from external high-speed oscillator (X1 and X2)
: Clock input from internal high-speed oscillator
: Clock input from external low-speed oscillator (XT1 and XT2)
: High-speed clock specified by CGOSCCR<OSCSEL>
: Clock quadrupled by PLL
: High-speed clock specified by CGPLLSEL<PLLSEL>
: High-speed clock specified by CGSYSCR<GEAR2:0>
: The same clock as fgear (system clock)
: Prescaler clock specified by CGSYSCR<PRCK2:0>
fc = fosc2
fsys = fc (=fosc2)
fperiph = fc (=fosc2)
ΦT0 = fperiph (=fosc2)
TMPM380/M382 - 9 / 24
: ON (oscillating)
: OFF (stop) XT1,XT2
: OFF (stop)
: fc (no frequency dividing)
TMPM380/M382
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